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インテル® FPGA設計に関する記事を投稿しよう! by インテル Advent Calendar 2022

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概要

FPGA(Field Programmable Gate Array)をご存知でしょうか?FPGAはハードウェアの中身(回路構成)を書き換えることができるユニークな半導体ICです。用途としてはHPC(High Peformance Computing)やネットワーク、組み込み機器まで様々です。FPGAの開発はハードウェアからソフトウェアまで様々なレイヤーが絡み合うため多くのことを学べます!

今回はインテル製品の中においても特徴的なFPGAの設計に関する記事を募集しています。今回を機に初挑戦の方から開発経験のある方まで経験や知見をご紹介ください!

こんな人におすすめ

  • FPGAに興味がある/使ってみたい方
  • インテル® FPGAでの開発経験がある方
  • ハードウェア開発経験がある方
  • ハードウェアオフロードしてみたい方

参考記事

参加方法・流れ

①本ページのカレンダーから、投稿したい日付の「参加登録」ボタンをクリック
②期間中(2022/12/1〜2022/12/25)に記事投稿した後、URLをカレンダーに紐付ける
③プレゼント対象者を決定
④Qiita運営チームより、2023/1/20(金)にライブ配信で受賞者を発表
⑤Qiita運営チームより、プレゼント対象者に連絡、発送(2023年1月下旬〜)

※過去の日付に遡って投稿可能です。
※キャンペーンの流れについて、一部、変更になる可能性がございます

プレゼント・選出基準

優秀賞 4名様

AirPods Pro(第2世代)

記事投稿ルール

プレゼント選出対象は以下のルールに沿って投稿される記事となります。

  • インテル® FPGAに絡めた記事であること
  • アプリケーションにおいては実行用コマンド、ソースコード、実行ログ等が記載されていること
  • 対象となるツール等のバージョンが古すぎないこと
  • 2022年12月(記事投稿)時点で再現性がとれること

PR

インテル® FPGA設計に関する記事を投稿いただくと、優秀賞として4名の方にAirPods Pro(第2世代)をプレゼントいたします。この機会に奮ってご参加ください。

終わりに

ぜひ皆さまの投稿と登録をよろしくお願いします!

Calendar1
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初心者のトークなので1発目貰おうかな。授業でFPGAを使った程度の大学生による振り返りを含めた紹介。簡単な紹介とか経験談を書くと思います。

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外部からPlatformDesignerモジュールにアクセスしよう~Avalon-MMブリッジの使い方あれこれ

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Python で SoC を操作し、L チカさせてみた

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Nios V Command Shell を使いやすく改造する(Windows Power Shell で起動)

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Cyclone® V SoC に載せるLinuxの構築手順

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Quartus Prime Lite Edition で Nios V が使えるか試してみる

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oneAPIを試してみるシーズン2

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9

浮動小数点例外の検出(ソフトウェア・コードとモデルベースFPGAデザイン)

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E-Tile + Nios V + lwIP でTCP/IP 通信を行う

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12

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オンボードメモリのデバッグ

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インテル® Agilex™ FPGA ベースの SmartNIC N6000-PLを使ってみた

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17

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18

マイコンでインテル® FPGA のコンフィグレーション ROM をアップデート! ~ NXP i.MX RT1050 編 ~

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19

OpenCL 試して見るかも

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20

AXI BFMを使ってシミュレーションしてみる

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21

インテル® Agilex™ で Nios V をたくさん実装してみた

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22

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23

verilog HDL design

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24

Simulink 物理モデル(water tank)と制御回路を DSP Builder で FPGA に実装 "model in FPGA"

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25

映像伝送機器間の同期~高精度なIP時刻同期プロトコル~

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1
初心者のトークなので1発目貰おうかな。授業でFPGAを使った程度の大学生による振り返りを含めた紹介。簡単な紹介とか経験談を書くと思います。

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2
外部からPlatformDesignerモジュールにアクセスしよう~Avalon-MMブリッジの使い方あれこれ

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3
Python で SoC を操作し、L チカさせてみた

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4
Nios V Command Shell を使いやすく改造する(Windows Power Shell で起動)

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5
Cyclone® V SoC に載せるLinuxの構築手順

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6
Quartus Prime Lite Edition で Nios V が使えるか試してみる

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7

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8
oneAPIを試してみるシーズン2

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9
浮動小数点例外の検出(ソフトウェア・コードとモデルベースFPGAデザイン)

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10
E-Tile + Nios V + lwIP でTCP/IP 通信を行う

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11

Join calendar on 11 day

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12

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オンボードメモリのデバッグ

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インテル® Agilex™ FPGA ベースの SmartNIC N6000-PLを使ってみた

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17

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18
マイコンでインテル® FPGA のコンフィグレーション ROM をアップデート! ~ NXP i.MX RT1050 編 ~

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19
OpenCL 試して見るかも

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20
AXI BFMを使ってシミュレーションしてみる

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21
インテル® Agilex™ で Nios V をたくさん実装してみた

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22

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23
verilog HDL design

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24
Simulink 物理モデル(water tank)と制御回路を DSP Builder で FPGA に実装 "model in FPGA"

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25
映像伝送機器間の同期~高精度なIP時刻同期プロトコル~

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初心者のトークなので1発目貰おうかな。授業でFPGAを使った程度の大学生による振り返りを含めた紹介。簡単な紹介とか経験談を書くと思います。

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外部からPlatformDesignerモジュールにアクセスしよう~Avalon-MMブリッジの使い方あれこれ

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Python で SoC を操作し、L チカさせてみた

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4

Nios V Command Shell を使いやすく改造する(Windows Power Shell で起動)

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5

Cyclone® V SoC に載せるLinuxの構築手順

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Quartus Prime Lite Edition で Nios V が使えるか試してみる

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7

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8

oneAPIを試してみるシーズン2

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9

浮動小数点例外の検出(ソフトウェア・コードとモデルベースFPGAデザイン)

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E-Tile + Nios V + lwIP でTCP/IP 通信を行う

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11

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12

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オンボードメモリのデバッグ

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16

インテル® Agilex™ FPGA ベースの SmartNIC N6000-PLを使ってみた

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17

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18

マイコンでインテル® FPGA のコンフィグレーション ROM をアップデート! ~ NXP i.MX RT1050 編 ~

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19

OpenCL 試して見るかも

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20

AXI BFMを使ってシミュレーションしてみる

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21

インテル® Agilex™ で Nios V をたくさん実装してみた

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22

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23

verilog HDL design

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24

Simulink 物理モデル(water tank)と制御回路を DSP Builder で FPGA に実装 "model in FPGA"

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25

映像伝送機器間の同期~高精度なIP時刻同期プロトコル~

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26

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1
初心者のトークなので1発目貰おうかな。授業でFPGAを使った程度の大学生による振り返りを含めた紹介。簡単な紹介とか経験談を書くと思います。

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2
外部からPlatformDesignerモジュールにアクセスしよう~Avalon-MMブリッジの使い方あれこれ

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3
Python で SoC を操作し、L チカさせてみた

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4
Nios V Command Shell を使いやすく改造する(Windows Power Shell で起動)

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5
Cyclone® V SoC に載せるLinuxの構築手順

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6
Quartus Prime Lite Edition で Nios V が使えるか試してみる

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7

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8
oneAPIを試してみるシーズン2

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9
浮動小数点例外の検出(ソフトウェア・コードとモデルベースFPGAデザイン)

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10
E-Tile + Nios V + lwIP でTCP/IP 通信を行う

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11

Join calendar on 11 day

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12

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13
オンボードメモリのデバッグ

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14

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15

Join calendar on 15 day

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16
インテル® Agilex™ FPGA ベースの SmartNIC N6000-PLを使ってみた

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17

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18
マイコンでインテル® FPGA のコンフィグレーション ROM をアップデート! ~ NXP i.MX RT1050 編 ~

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19
OpenCL 試して見るかも

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20
AXI BFMを使ってシミュレーションしてみる

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21
インテル® Agilex™ で Nios V をたくさん実装してみた

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22

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23
verilog HDL design

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24
Simulink 物理モデル(water tank)と制御回路を DSP Builder で FPGA に実装 "model in FPGA"

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25
映像伝送機器間の同期~高精度なIP時刻同期プロトコル~

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