目次
はじめに
こんにちは。株式会社フィックスターズ の 望月 英輔 と申します。
手元にあったES 品のIntel Agilex F-Series FPGA Development Kit を使用してTCP/IP 通信を行いました。
通信に必要なハードウェアはボード上に揃っているので、FPGA 上に通信するためのデザインを構築した手順を紹介します。
Intel FPGA でTCP/IP 通信を行うには
Intel FPGA でTCP/IP 通信を行いたい場合、Nios® V Processor - Using the MicroC/TCP-IP Stack を利用する方法が挙げられます。
Intel 公式でサポートしているものなので、とりあえず動かしてみるにはこちらを選択するのがベターです。
ただ今回は、OS なしで軽量に動作させたかったのと、単純にそれだけでは面白くないと思ったので、Nios V 上で軽量なTCP/IP プロトコル・スタック実装であるlwIP を動作させる、以下のような構成としました。
このような構成としたのは、
- E-Tile とのデータのやり取りはStream で行われる
- Nios V とのデータのやり取りはMemory Map で行いたい
という事情があり、Stream とMemory Map を変換するFIFO Memory を配置したという経緯があるためです。
Nios V からMemory Map でデータにアクセスできるようになれば、あとはNios V で動作するコードの開発を行えばよいので、FPGA 側はそれ以上の機能を有していません。
以下に用語の簡単な解説を記載しますので、併せてご覧ください。
Nios V
Intel FPGA に実装可能なRISC-V ソフトコア・プロセッサです。
今回はlwIP を動作させるために使用します。
詳細は Nios® V プロセッサー - インテル® FPGA をご覧ください
lwIP (lightweight IP)
オープンソースの軽量なTCP/IP プロトコル・スタック実装です。
今回はこちらをNios V 上で動作させ、TCP/IP 通信を実現します。
詳細は lwIP - A Lightweight TCP_IP stack - Summary [Savannah] をご覧ください。
E-Tile
Stratix 10, Agilex に搭載されている高速トランシーバーです。
インテル ® FPGA E タイル・トランシーバー 紹介 – 株式会社マクニカ アルティマ カンパニー に詳しい記載があります。
今回は10/25/100Gbps のEthernet として利用可能な"E-Tile Ethernet IP"の一部として使用します。
詳細は インテル® Agilex™ およびインテル® Stratix® 10 FPGA E タイル・ハード IP をご覧ください。
FIFO Memory
E-Tile Ethernet IP へStream で入出力されるデータを、Nios V がアクセス可能なMemory Map 方式に変換するためのFIFO です。
詳細は 24. インテルFPGA Avalon FIFOメモリーコア をご覧ください。
QSFPDD
最大400Gbps での通信が可能なコネクタシステムです。
400G時代を見据えたモジュール/ケージ/コネクタシステム「QSFP-DD」 :: JANOG40 に詳しい記載があります。
FPGA の実装
E-Tile Ethernet IP, FIFO Memory, Nios V をFPGA 上に実装します。
いずれもIntel 純正で用意されているIP だったため、Platform Designer を利用しました。
クロック乗り換えやAvalon-ST の幅変換、Nios V 用のメモリ等IP が追加されていますが、構成自体は「Intel FPGA でTCP/IP 通信を行うには」の図と同様です。
図だけだと各IP の設定が分からないので、tcl スクリプト化したものを用意しました。
sys.tcl を下記コマンドで展開すると、Platform Designer で中身を確認できます。
# sys.tcl を展開
$ qsys-script --script=sys.tcl
# Platform Designer で確認
$ qsys-edit sys.qsys -qpf=sys.qpf
sys.tcl
sys.tcl
package require -exact qsys 21.3
# create the system "sys"
proc do_create_sys {} {
# create the system
create_system sys
set_project_property DEVICE {AGFB014R24A2E3VR0}
set_project_property DEVICE_FAMILY {Agilex}
set_project_property HIDE_FROM_IP_CATALOG {false}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_component rx_clk_converter ip/sys/sys_hs_clk_xer_1.ip hs_clk_xer hs_clk_xer_1 19.3.1
load_component rx_clk_converter
set_component_parameter_value BITS_PER_SYMBOL {8}
set_component_parameter_value CHANNEL_WIDTH {1}
set_component_parameter_value DATA_WIDTH {512}
set_component_parameter_value ERROR_WIDTH {1}
set_component_parameter_value MAX_CHANNEL {0}
set_component_parameter_value READY_SYNC_DEPTH {2}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_CHANNEL {0}
set_component_parameter_value USE_ERROR {0}
set_component_parameter_value USE_OUTPUT_PIPELINE {1}
set_component_parameter_value USE_PACKETS {1}
set_component_parameter_value VALID_SYNC_DEPTH {2}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation rx_clk_converter
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_clk clock INPUT
set_instantiation_interface_parameter_value in_clk clockRate {0}
set_instantiation_interface_parameter_value in_clk externallyDriven {false}
set_instantiation_interface_parameter_value in_clk ptfSchematicName {}
add_instantiation_interface_port in_clk in_clk clk 1 STD_LOGIC Input
add_instantiation_interface in_clk_reset reset INPUT
set_instantiation_interface_parameter_value in_clk_reset associatedClock {in_clk}
set_instantiation_interface_parameter_value in_clk_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port in_clk_reset in_reset reset 1 STD_LOGIC Input
add_instantiation_interface out_clk clock INPUT
set_instantiation_interface_parameter_value out_clk clockRate {0}
set_instantiation_interface_parameter_value out_clk externallyDriven {false}
set_instantiation_interface_parameter_value out_clk ptfSchematicName {}
add_instantiation_interface_port out_clk out_clk clk 1 STD_LOGIC Input
add_instantiation_interface out_clk_reset reset INPUT
set_instantiation_interface_parameter_value out_clk_reset associatedClock {out_clk}
set_instantiation_interface_parameter_value out_clk_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port out_clk_reset out_reset reset 1 STD_LOGIC Input
add_instantiation_interface in avalon_streaming INPUT
set_instantiation_interface_parameter_value in associatedClock {in_clk}
set_instantiation_interface_parameter_value in associatedReset {in_clk_reset}
set_instantiation_interface_parameter_value in beatsPerCycle {1}
set_instantiation_interface_parameter_value in dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in emptyWithinPacket {false}
set_instantiation_interface_parameter_value in errorDescriptor {}
set_instantiation_interface_parameter_value in firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in maxChannel {0}
set_instantiation_interface_parameter_value in packetDescription {}
set_instantiation_interface_parameter_value in prSafe {false}
set_instantiation_interface_parameter_value in readyAllowance {0}
set_instantiation_interface_parameter_value in readyLatency {0}
set_instantiation_interface_parameter_value in symbolsPerBeat {1}
add_instantiation_interface_port in in_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port in in_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in in_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_empty empty 6 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in in_data data 512 STD_LOGIC_VECTOR Input
add_instantiation_interface out avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out associatedClock {out_clk}
set_instantiation_interface_parameter_value out associatedReset {out_clk_reset}
set_instantiation_interface_parameter_value out beatsPerCycle {1}
set_instantiation_interface_parameter_value out dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out emptyWithinPacket {false}
set_instantiation_interface_parameter_value out errorDescriptor {}
set_instantiation_interface_parameter_value out firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out maxChannel {0}
set_instantiation_interface_parameter_value out packetDescription {}
set_instantiation_interface_parameter_value out prSafe {false}
set_instantiation_interface_parameter_value out readyAllowance {0}
set_instantiation_interface_parameter_value out readyLatency {0}
set_instantiation_interface_parameter_value out symbolsPerBeat {1}
add_instantiation_interface_port out out_ready ready 1 STD_LOGIC Input
add_instantiation_interface_port out out_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out out_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_empty empty 6 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out out_data data 512 STD_LOGIC_VECTOR Output
save_instantiation
add_component rx_rst_bridge ip/sys/sys_rst_bridge.ip altera_reset_bridge sys_rst_bridge 19.2.0
load_component rx_rst_bridge
set_component_parameter_value ACTIVE_LOW_RESET {0}
set_component_parameter_value NUM_RESET_OUTPUTS {1}
set_component_parameter_value SYNCHRONOUS_EDGES {none}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_RESET_REQUEST {0}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation rx_rst_bridge
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_reset reset INPUT
set_instantiation_interface_parameter_value in_reset associatedClock {}
set_instantiation_interface_parameter_value in_reset synchronousEdges {NONE}
add_instantiation_interface_port in_reset in_reset reset 1 STD_LOGIC Input
add_instantiation_interface out_reset reset OUTPUT
set_instantiation_interface_parameter_value out_reset associatedClock {}
set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset}
set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset}
set_instantiation_interface_parameter_value out_reset synchronousEdges {NONE}
add_instantiation_interface_port out_reset out_reset reset 1 STD_LOGIC Output
save_instantiation
add_component st_dc_fifo_rx ip/sys/sys_sc_fifo_1.ip altera_avalon_sc_fifo sc_fifo_1 19.3.1
load_component st_dc_fifo_rx
set_component_parameter_value BITS_PER_SYMBOL {8}
set_component_parameter_value CHANNEL_WIDTH {0}
set_component_parameter_value EMPTY_LATENCY {3}
set_component_parameter_value ENABLE_EXPLICIT_MAXCHANNEL {0}
set_component_parameter_value ERROR_WIDTH {0}
set_component_parameter_value EXPLICIT_MAXCHANNEL {0}
set_component_parameter_value FIFO_DEPTH {1024}
set_component_parameter_value SYMBOLS_PER_BEAT {64}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_ALMOST_EMPTY_IF {0}
set_component_parameter_value USE_ALMOST_FULL_IF {1}
set_component_parameter_value USE_FILL_LEVEL {1}
set_component_parameter_value USE_MEMORY_BLOCKS {1}
set_component_parameter_value USE_PACKETS {1}
set_component_parameter_value USE_STORE_FORWARD {0}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation st_dc_fifo_rx
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value debug.isTransparent {1}
add_instantiation_interface clk clock INPUT
set_instantiation_interface_parameter_value clk clockRate {0}
set_instantiation_interface_parameter_value clk externallyDriven {false}
set_instantiation_interface_parameter_value clk ptfSchematicName {}
add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input
add_instantiation_interface clk_reset reset INPUT
set_instantiation_interface_parameter_value clk_reset associatedClock {clk}
set_instantiation_interface_parameter_value clk_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port clk_reset reset reset 1 STD_LOGIC Input
add_instantiation_interface csr avalon INPUT
set_instantiation_interface_parameter_value csr addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value csr addressGroup {0}
set_instantiation_interface_parameter_value csr addressSpan {16}
set_instantiation_interface_parameter_value csr addressUnits {WORDS}
set_instantiation_interface_parameter_value csr alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value csr associatedClock {clk}
set_instantiation_interface_parameter_value csr associatedReset {clk_reset}
set_instantiation_interface_parameter_value csr bitsPerSymbol {8}
set_instantiation_interface_parameter_value csr bridgedAddressOffset {0}
set_instantiation_interface_parameter_value csr bridgesToMaster {}
set_instantiation_interface_parameter_value csr burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value csr burstcountUnits {WORDS}
set_instantiation_interface_parameter_value csr constantBurstBehavior {false}
set_instantiation_interface_parameter_value csr explicitAddressSpan {0}
set_instantiation_interface_parameter_value csr holdTime {0}
set_instantiation_interface_parameter_value csr interleaveBursts {false}
set_instantiation_interface_parameter_value csr isBigEndian {false}
set_instantiation_interface_parameter_value csr isFlash {false}
set_instantiation_interface_parameter_value csr isMemoryDevice {false}
set_instantiation_interface_parameter_value csr isNonVolatileStorage {false}
set_instantiation_interface_parameter_value csr linewrapBursts {false}
set_instantiation_interface_parameter_value csr maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value csr maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value csr minimumReadLatency {1}
set_instantiation_interface_parameter_value csr minimumResponseLatency {1}
set_instantiation_interface_parameter_value csr minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value csr prSafe {false}
set_instantiation_interface_parameter_value csr printableDevice {false}
set_instantiation_interface_parameter_value csr readLatency {1}
set_instantiation_interface_parameter_value csr readWaitStates {0}
set_instantiation_interface_parameter_value csr readWaitTime {0}
set_instantiation_interface_parameter_value csr registerIncomingSignals {false}
set_instantiation_interface_parameter_value csr registerOutgoingSignals {false}
set_instantiation_interface_parameter_value csr setupTime {0}
set_instantiation_interface_parameter_value csr timingUnits {Cycles}
set_instantiation_interface_parameter_value csr transparentBridge {false}
set_instantiation_interface_parameter_value csr waitrequestAllowance {0}
set_instantiation_interface_parameter_value csr wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value csr writeLatency {0}
set_instantiation_interface_parameter_value csr writeWaitStates {0}
set_instantiation_interface_parameter_value csr writeWaitTime {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value csr address_map {<address-map><slave name='csr' start='0x0' end='0x10' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value csr address_width {4}
set_instantiation_interface_sysinfo_parameter_value csr max_slave_data_width {32}
add_instantiation_interface_port csr csr_address address 2 STD_LOGIC_VECTOR Input
add_instantiation_interface_port csr csr_read read 1 STD_LOGIC Input
add_instantiation_interface_port csr csr_write write 1 STD_LOGIC Input
add_instantiation_interface_port csr csr_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port csr csr_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface almost_full avalon_streaming OUTPUT
set_instantiation_interface_parameter_value almost_full associatedClock {clk}
set_instantiation_interface_parameter_value almost_full associatedReset {clk_reset}
set_instantiation_interface_parameter_value almost_full beatsPerCycle {1}
set_instantiation_interface_parameter_value almost_full dataBitsPerSymbol {1}
set_instantiation_interface_parameter_value almost_full emptyWithinPacket {false}
set_instantiation_interface_parameter_value almost_full errorDescriptor {}
set_instantiation_interface_parameter_value almost_full firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value almost_full highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value almost_full maxChannel {0}
set_instantiation_interface_parameter_value almost_full packetDescription {}
set_instantiation_interface_parameter_value almost_full prSafe {false}
set_instantiation_interface_parameter_value almost_full readyAllowance {0}
set_instantiation_interface_parameter_value almost_full readyLatency {0}
set_instantiation_interface_parameter_value almost_full symbolsPerBeat {1}
add_instantiation_interface_port almost_full almost_full_data data 1 STD_LOGIC Output
add_instantiation_interface in avalon_streaming INPUT
set_instantiation_interface_parameter_value in associatedClock {clk}
set_instantiation_interface_parameter_value in associatedReset {clk_reset}
set_instantiation_interface_parameter_value in beatsPerCycle {1}
set_instantiation_interface_parameter_value in dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in emptyWithinPacket {false}
set_instantiation_interface_parameter_value in errorDescriptor {}
set_instantiation_interface_parameter_value in firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in maxChannel {0}
set_instantiation_interface_parameter_value in packetDescription {}
set_instantiation_interface_parameter_value in prSafe {false}
set_instantiation_interface_parameter_value in readyAllowance {0}
set_instantiation_interface_parameter_value in readyLatency {0}
set_instantiation_interface_parameter_value in symbolsPerBeat {64}
add_instantiation_interface_port in in_data data 512 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in in_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in in_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port in in_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_empty empty 6 STD_LOGIC_VECTOR Input
add_instantiation_interface out avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out associatedClock {clk}
set_instantiation_interface_parameter_value out associatedReset {clk_reset}
set_instantiation_interface_parameter_value out beatsPerCycle {1}
set_instantiation_interface_parameter_value out dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out emptyWithinPacket {false}
set_instantiation_interface_parameter_value out errorDescriptor {}
set_instantiation_interface_parameter_value out firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out maxChannel {0}
set_instantiation_interface_parameter_value out packetDescription {}
set_instantiation_interface_parameter_value out prSafe {false}
set_instantiation_interface_parameter_value out readyAllowance {0}
set_instantiation_interface_parameter_value out readyLatency {0}
set_instantiation_interface_parameter_value out symbolsPerBeat {64}
set_instantiation_interface_assignment_value out debug.controlledBy {in}
add_instantiation_interface_port out out_data data 512 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out out_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out out_ready ready 1 STD_LOGIC Input
add_instantiation_interface_port out out_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_empty empty 6 STD_LOGIC_VECTOR Output
save_instantiation
add_component st_sc_fifo_tx ip/sys/sys_sc_fifo_0.ip altera_avalon_sc_fifo sc_fifo_0 19.3.1
load_component st_sc_fifo_tx
set_component_parameter_value BITS_PER_SYMBOL {8}
set_component_parameter_value CHANNEL_WIDTH {0}
set_component_parameter_value EMPTY_LATENCY {3}
set_component_parameter_value ENABLE_EXPLICIT_MAXCHANNEL {0}
set_component_parameter_value ERROR_WIDTH {0}
set_component_parameter_value EXPLICIT_MAXCHANNEL {0}
set_component_parameter_value FIFO_DEPTH {1024}
set_component_parameter_value SYMBOLS_PER_BEAT {64}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_ALMOST_EMPTY_IF {0}
set_component_parameter_value USE_ALMOST_FULL_IF {0}
set_component_parameter_value USE_FILL_LEVEL {1}
set_component_parameter_value USE_MEMORY_BLOCKS {1}
set_component_parameter_value USE_PACKETS {1}
set_component_parameter_value USE_STORE_FORWARD {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation st_sc_fifo_tx
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value debug.isTransparent {1}
add_instantiation_interface clk clock INPUT
set_instantiation_interface_parameter_value clk clockRate {0}
set_instantiation_interface_parameter_value clk externallyDriven {false}
set_instantiation_interface_parameter_value clk ptfSchematicName {}
add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input
add_instantiation_interface clk_reset reset INPUT
set_instantiation_interface_parameter_value clk_reset associatedClock {clk}
set_instantiation_interface_parameter_value clk_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port clk_reset reset reset 1 STD_LOGIC Input
add_instantiation_interface csr avalon INPUT
set_instantiation_interface_parameter_value csr addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value csr addressGroup {0}
set_instantiation_interface_parameter_value csr addressSpan {32}
set_instantiation_interface_parameter_value csr addressUnits {WORDS}
set_instantiation_interface_parameter_value csr alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value csr associatedClock {clk}
set_instantiation_interface_parameter_value csr associatedReset {clk_reset}
set_instantiation_interface_parameter_value csr bitsPerSymbol {8}
set_instantiation_interface_parameter_value csr bridgedAddressOffset {0}
set_instantiation_interface_parameter_value csr bridgesToMaster {}
set_instantiation_interface_parameter_value csr burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value csr burstcountUnits {WORDS}
set_instantiation_interface_parameter_value csr constantBurstBehavior {false}
set_instantiation_interface_parameter_value csr explicitAddressSpan {0}
set_instantiation_interface_parameter_value csr holdTime {0}
set_instantiation_interface_parameter_value csr interleaveBursts {false}
set_instantiation_interface_parameter_value csr isBigEndian {false}
set_instantiation_interface_parameter_value csr isFlash {false}
set_instantiation_interface_parameter_value csr isMemoryDevice {false}
set_instantiation_interface_parameter_value csr isNonVolatileStorage {false}
set_instantiation_interface_parameter_value csr linewrapBursts {false}
set_instantiation_interface_parameter_value csr maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value csr maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value csr minimumReadLatency {1}
set_instantiation_interface_parameter_value csr minimumResponseLatency {1}
set_instantiation_interface_parameter_value csr minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value csr prSafe {false}
set_instantiation_interface_parameter_value csr printableDevice {false}
set_instantiation_interface_parameter_value csr readLatency {1}
set_instantiation_interface_parameter_value csr readWaitStates {0}
set_instantiation_interface_parameter_value csr readWaitTime {0}
set_instantiation_interface_parameter_value csr registerIncomingSignals {false}
set_instantiation_interface_parameter_value csr registerOutgoingSignals {false}
set_instantiation_interface_parameter_value csr setupTime {0}
set_instantiation_interface_parameter_value csr timingUnits {Cycles}
set_instantiation_interface_parameter_value csr transparentBridge {false}
set_instantiation_interface_parameter_value csr waitrequestAllowance {0}
set_instantiation_interface_parameter_value csr wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value csr writeLatency {0}
set_instantiation_interface_parameter_value csr writeWaitStates {0}
set_instantiation_interface_parameter_value csr writeWaitTime {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value csr embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value csr address_map {<address-map><slave name='csr' start='0x0' end='0x20' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value csr address_width {5}
set_instantiation_interface_sysinfo_parameter_value csr max_slave_data_width {32}
add_instantiation_interface_port csr csr_address address 3 STD_LOGIC_VECTOR Input
add_instantiation_interface_port csr csr_read read 1 STD_LOGIC Input
add_instantiation_interface_port csr csr_write write 1 STD_LOGIC Input
add_instantiation_interface_port csr csr_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port csr csr_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface in avalon_streaming INPUT
set_instantiation_interface_parameter_value in associatedClock {clk}
set_instantiation_interface_parameter_value in associatedReset {clk_reset}
set_instantiation_interface_parameter_value in beatsPerCycle {1}
set_instantiation_interface_parameter_value in dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in emptyWithinPacket {false}
set_instantiation_interface_parameter_value in errorDescriptor {}
set_instantiation_interface_parameter_value in firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in maxChannel {0}
set_instantiation_interface_parameter_value in packetDescription {}
set_instantiation_interface_parameter_value in prSafe {false}
set_instantiation_interface_parameter_value in readyAllowance {0}
set_instantiation_interface_parameter_value in readyLatency {0}
set_instantiation_interface_parameter_value in symbolsPerBeat {64}
add_instantiation_interface_port in in_data data 512 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in in_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in in_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port in in_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_empty empty 6 STD_LOGIC_VECTOR Input
add_instantiation_interface out avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out associatedClock {clk}
set_instantiation_interface_parameter_value out associatedReset {clk_reset}
set_instantiation_interface_parameter_value out beatsPerCycle {1}
set_instantiation_interface_parameter_value out dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out emptyWithinPacket {false}
set_instantiation_interface_parameter_value out errorDescriptor {}
set_instantiation_interface_parameter_value out firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out maxChannel {0}
set_instantiation_interface_parameter_value out packetDescription {}
set_instantiation_interface_parameter_value out prSafe {false}
set_instantiation_interface_parameter_value out readyAllowance {0}
set_instantiation_interface_parameter_value out readyLatency {0}
set_instantiation_interface_parameter_value out symbolsPerBeat {64}
set_instantiation_interface_assignment_value out debug.controlledBy {in}
add_instantiation_interface_port out out_data data 512 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out out_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out out_ready ready 1 STD_LOGIC Input
add_instantiation_interface_port out out_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_empty empty 6 STD_LOGIC_VECTOR Output
save_instantiation
add_component sys_clk_bridge ip/sys/sys_clk_bridge.ip altera_clock_bridge sys_clk_bridge 19.2.0
load_component sys_clk_bridge
set_component_parameter_value EXPLICIT_CLOCK_RATE {100000000.0}
set_component_parameter_value NUM_CLOCK_OUTPUTS {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_clk_bridge
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_clk clock INPUT
set_instantiation_interface_parameter_value in_clk clockRate {0}
set_instantiation_interface_parameter_value in_clk externallyDriven {false}
set_instantiation_interface_parameter_value in_clk ptfSchematicName {}
add_instantiation_interface_port in_clk in_clk clk 1 STD_LOGIC Input
add_instantiation_interface out_clk clock OUTPUT
set_instantiation_interface_parameter_value out_clk associatedDirectClock {in_clk}
set_instantiation_interface_parameter_value out_clk clockRate {100000000}
set_instantiation_interface_parameter_value out_clk clockRateKnown {true}
set_instantiation_interface_parameter_value out_clk externallyDriven {false}
set_instantiation_interface_parameter_value out_clk ptfSchematicName {}
set_instantiation_interface_sysinfo_parameter_value out_clk clock_rate {100000000}
add_instantiation_interface_port out_clk out_clk clk 1 STD_LOGIC Output
save_instantiation
add_component sys_cpu ip/sys/sys_cpu.ip intel_niosv_m sys_cpu 21.3.0
load_component sys_cpu
set_component_parameter_value enableDebug {1}
set_component_parameter_value exceptionOffset {32}
set_component_parameter_value exceptionSlave {sys_cpu_ram.s1}
set_component_parameter_value numGpr {32}
set_component_parameter_value resetOffset {0}
set_component_parameter_value resetSlave {sys_cpu_ram.s1}
set_component_parameter_value useResetReq {0}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_cpu
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.CMacro.CPU_FREQ {300000000u}
set_instantiation_assignment_value embeddedsw.CMacro.DATA_ADDR_WIDTH {32}
set_instantiation_assignment_value embeddedsw.CMacro.DCACHE_LINE_SIZE {0}
set_instantiation_assignment_value embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 {0}
set_instantiation_assignment_value embeddedsw.CMacro.DCACHE_SIZE {0}
set_instantiation_assignment_value embeddedsw.CMacro.EXCEPTION_ADDR {0x00000020}
set_instantiation_assignment_value embeddedsw.CMacro.HAS_DEBUG_STUB {}
set_instantiation_assignment_value embeddedsw.CMacro.ICACHE_LINE_SIZE {0}
set_instantiation_assignment_value embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 {0}
set_instantiation_assignment_value embeddedsw.CMacro.ICACHE_SIZE {0}
set_instantiation_assignment_value embeddedsw.CMacro.INST_ADDR_WIDTH {32}
set_instantiation_assignment_value embeddedsw.CMacro.MTIME_OFFSET {0x00210000}
set_instantiation_assignment_value embeddedsw.CMacro.NUM_GPR {32}
set_instantiation_assignment_value embeddedsw.CMacro.RESET_ADDR {0x00000000}
set_instantiation_assignment_value embeddedsw.CMacro.TICKS_PER_SEC {no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)}
set_instantiation_assignment_value embeddedsw.CMacro.TIMER_DEVICE_TYPE {2}
set_instantiation_assignment_value embeddedsw.configuration.HDLSimCachesCleared {1}
set_instantiation_assignment_value embeddedsw.configuration.cpuArchitecture {Abbotts Lake}
set_instantiation_assignment_value embeddedsw.configuration.exceptionOffset {32}
set_instantiation_assignment_value embeddedsw.configuration.exceptionSlave {sys_cpu_ram.s1}
set_instantiation_assignment_value embeddedsw.configuration.isTimerDevice {1}
set_instantiation_assignment_value embeddedsw.configuration.numGpr {32}
set_instantiation_assignment_value embeddedsw.configuration.resetOffset {0}
set_instantiation_assignment_value embeddedsw.configuration.resetSlave {sys_cpu_ram.s1}
set_instantiation_assignment_value embeddedsw.dts.params.altr,exception-addr {0x00000020}
set_instantiation_assignment_value embeddedsw.dts.params.altr,reset-addr {0x00000000}
set_instantiation_assignment_value embeddedsw.dts.params.clock-frequency {300000000u}
set_instantiation_assignment_value embeddedsw.dts.params.dcache-line-size {0}
set_instantiation_assignment_value embeddedsw.dts.params.dcache-size {0}
set_instantiation_assignment_value embeddedsw.dts.params.icache-line-size {0}
set_instantiation_assignment_value embeddedsw.dts.params.icache-size {0}
add_instantiation_interface clk clock INPUT
set_instantiation_interface_parameter_value clk clockRate {0}
set_instantiation_interface_parameter_value clk externallyDriven {false}
set_instantiation_interface_parameter_value clk ptfSchematicName {}
add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input
add_instantiation_interface reset reset INPUT
set_instantiation_interface_parameter_value reset associatedClock {clk}
set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT}
add_instantiation_interface_port reset reset_reset reset 1 STD_LOGIC Input
add_instantiation_interface platform_irq_rx interrupt OUTPUT
set_instantiation_interface_parameter_value platform_irq_rx associatedAddressablePoint {}
set_instantiation_interface_parameter_value platform_irq_rx associatedClock {clk}
set_instantiation_interface_parameter_value platform_irq_rx associatedReset {reset}
set_instantiation_interface_parameter_value platform_irq_rx irqMap {}
set_instantiation_interface_parameter_value platform_irq_rx irqScheme {INDIVIDUAL_REQUESTS}
add_instantiation_interface_port platform_irq_rx platform_irq_rx_irq irq 16 STD_LOGIC_VECTOR Input
add_instantiation_interface instruction_manager axi4 OUTPUT
set_instantiation_interface_parameter_value instruction_manager associatedClock {clk}
set_instantiation_interface_parameter_value instruction_manager associatedReset {reset}
set_instantiation_interface_parameter_value instruction_manager combinedIssuingCapability {2}
set_instantiation_interface_parameter_value instruction_manager issuesFIXEDBursts {true}
set_instantiation_interface_parameter_value instruction_manager issuesINCRBursts {true}
set_instantiation_interface_parameter_value instruction_manager issuesWRAPBursts {true}
set_instantiation_interface_parameter_value instruction_manager maximumOutstandingReads {1}
set_instantiation_interface_parameter_value instruction_manager maximumOutstandingTransactions {1}
set_instantiation_interface_parameter_value instruction_manager maximumOutstandingWrites {1}
set_instantiation_interface_parameter_value instruction_manager readIssuingCapability {2}
set_instantiation_interface_parameter_value instruction_manager trustzoneAware {true}
set_instantiation_interface_parameter_value instruction_manager writeIssuingCapability {1}
add_instantiation_interface_port instruction_manager instruction_manager_awaddr awaddr 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_awsize awsize 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_awprot awprot 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_awvalid awvalid 1 STD_LOGIC Output
add_instantiation_interface_port instruction_manager instruction_manager_awready awready 1 STD_LOGIC Input
add_instantiation_interface_port instruction_manager instruction_manager_wdata wdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_wstrb wstrb 4 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_wlast wlast 1 STD_LOGIC Output
add_instantiation_interface_port instruction_manager instruction_manager_wvalid wvalid 1 STD_LOGIC Output
add_instantiation_interface_port instruction_manager instruction_manager_wready wready 1 STD_LOGIC Input
add_instantiation_interface_port instruction_manager instruction_manager_bresp bresp 2 STD_LOGIC_VECTOR Input
add_instantiation_interface_port instruction_manager instruction_manager_bvalid bvalid 1 STD_LOGIC Input
add_instantiation_interface_port instruction_manager instruction_manager_bready bready 1 STD_LOGIC Output
add_instantiation_interface_port instruction_manager instruction_manager_araddr araddr 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_arsize arsize 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_arprot arprot 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port instruction_manager instruction_manager_arvalid arvalid 1 STD_LOGIC Output
add_instantiation_interface_port instruction_manager instruction_manager_arready arready 1 STD_LOGIC Input
add_instantiation_interface_port instruction_manager instruction_manager_rdata rdata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port instruction_manager instruction_manager_rresp rresp 2 STD_LOGIC_VECTOR Input
add_instantiation_interface_port instruction_manager instruction_manager_rvalid rvalid 1 STD_LOGIC Input
add_instantiation_interface_port instruction_manager instruction_manager_rready rready 1 STD_LOGIC Output
add_instantiation_interface data_manager axi4 OUTPUT
set_instantiation_interface_parameter_value data_manager associatedClock {clk}
set_instantiation_interface_parameter_value data_manager associatedReset {reset}
set_instantiation_interface_parameter_value data_manager combinedIssuingCapability {1}
set_instantiation_interface_parameter_value data_manager issuesFIXEDBursts {true}
set_instantiation_interface_parameter_value data_manager issuesINCRBursts {true}
set_instantiation_interface_parameter_value data_manager issuesWRAPBursts {true}
set_instantiation_interface_parameter_value data_manager maximumOutstandingReads {1}
set_instantiation_interface_parameter_value data_manager maximumOutstandingTransactions {1}
set_instantiation_interface_parameter_value data_manager maximumOutstandingWrites {1}
set_instantiation_interface_parameter_value data_manager readIssuingCapability {1}
set_instantiation_interface_parameter_value data_manager trustzoneAware {true}
set_instantiation_interface_parameter_value data_manager writeIssuingCapability {1}
add_instantiation_interface_port data_manager data_manager_awaddr awaddr 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_awsize awsize 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_awprot awprot 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_awvalid awvalid 1 STD_LOGIC Output
add_instantiation_interface_port data_manager data_manager_awready awready 1 STD_LOGIC Input
add_instantiation_interface_port data_manager data_manager_wdata wdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_wstrb wstrb 4 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_wlast wlast 1 STD_LOGIC Output
add_instantiation_interface_port data_manager data_manager_wvalid wvalid 1 STD_LOGIC Output
add_instantiation_interface_port data_manager data_manager_wready wready 1 STD_LOGIC Input
add_instantiation_interface_port data_manager data_manager_bresp bresp 2 STD_LOGIC_VECTOR Input
add_instantiation_interface_port data_manager data_manager_bvalid bvalid 1 STD_LOGIC Input
add_instantiation_interface_port data_manager data_manager_bready bready 1 STD_LOGIC Output
add_instantiation_interface_port data_manager data_manager_araddr araddr 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_arsize arsize 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_arprot arprot 3 STD_LOGIC_VECTOR Output
add_instantiation_interface_port data_manager data_manager_arvalid arvalid 1 STD_LOGIC Output
add_instantiation_interface_port data_manager data_manager_arready arready 1 STD_LOGIC Input
add_instantiation_interface_port data_manager data_manager_rdata rdata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port data_manager data_manager_rresp rresp 2 STD_LOGIC_VECTOR Input
add_instantiation_interface_port data_manager data_manager_rvalid rvalid 1 STD_LOGIC Input
add_instantiation_interface_port data_manager data_manager_rready rready 1 STD_LOGIC Output
add_instantiation_interface timer_sw_agent avalon INPUT
set_instantiation_interface_parameter_value timer_sw_agent addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value timer_sw_agent addressGroup {0}
set_instantiation_interface_parameter_value timer_sw_agent addressSpan {64}
set_instantiation_interface_parameter_value timer_sw_agent addressUnits {SYMBOLS}
set_instantiation_interface_parameter_value timer_sw_agent alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value timer_sw_agent associatedClock {clk}
set_instantiation_interface_parameter_value timer_sw_agent associatedReset {reset}
set_instantiation_interface_parameter_value timer_sw_agent bitsPerSymbol {8}
set_instantiation_interface_parameter_value timer_sw_agent bridgedAddressOffset {0}
set_instantiation_interface_parameter_value timer_sw_agent bridgesToMaster {}
set_instantiation_interface_parameter_value timer_sw_agent burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value timer_sw_agent burstcountUnits {WORDS}
set_instantiation_interface_parameter_value timer_sw_agent constantBurstBehavior {false}
set_instantiation_interface_parameter_value timer_sw_agent explicitAddressSpan {0}
set_instantiation_interface_parameter_value timer_sw_agent holdTime {0}
set_instantiation_interface_parameter_value timer_sw_agent interleaveBursts {false}
set_instantiation_interface_parameter_value timer_sw_agent isBigEndian {false}
set_instantiation_interface_parameter_value timer_sw_agent isFlash {false}
set_instantiation_interface_parameter_value timer_sw_agent isMemoryDevice {false}
set_instantiation_interface_parameter_value timer_sw_agent isNonVolatileStorage {false}
set_instantiation_interface_parameter_value timer_sw_agent linewrapBursts {false}
set_instantiation_interface_parameter_value timer_sw_agent maximumPendingReadTransactions {2}
set_instantiation_interface_parameter_value timer_sw_agent maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value timer_sw_agent minimumReadLatency {1}
set_instantiation_interface_parameter_value timer_sw_agent minimumResponseLatency {1}
set_instantiation_interface_parameter_value timer_sw_agent minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value timer_sw_agent prSafe {false}
set_instantiation_interface_parameter_value timer_sw_agent printableDevice {false}
set_instantiation_interface_parameter_value timer_sw_agent readLatency {0}
set_instantiation_interface_parameter_value timer_sw_agent readWaitStates {1}
set_instantiation_interface_parameter_value timer_sw_agent readWaitTime {1}
set_instantiation_interface_parameter_value timer_sw_agent registerIncomingSignals {false}
set_instantiation_interface_parameter_value timer_sw_agent registerOutgoingSignals {false}
set_instantiation_interface_parameter_value timer_sw_agent setupTime {0}
set_instantiation_interface_parameter_value timer_sw_agent timingUnits {Cycles}
set_instantiation_interface_parameter_value timer_sw_agent transparentBridge {false}
set_instantiation_interface_parameter_value timer_sw_agent waitrequestAllowance {0}
set_instantiation_interface_parameter_value timer_sw_agent wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value timer_sw_agent writeLatency {0}
set_instantiation_interface_parameter_value timer_sw_agent writeWaitStates {0}
set_instantiation_interface_parameter_value timer_sw_agent writeWaitTime {0}
set_instantiation_interface_assignment_value timer_sw_agent embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value timer_sw_agent embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value timer_sw_agent embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value timer_sw_agent embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_assignment_value timer_sw_agent qsys.ui.connect {data_manager}
set_instantiation_interface_sysinfo_parameter_value timer_sw_agent address_map {<address-map><slave name='timer_sw_agent' start='0x0' end='0x40' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value timer_sw_agent address_width {6}
set_instantiation_interface_sysinfo_parameter_value timer_sw_agent max_slave_data_width {32}
add_instantiation_interface_port timer_sw_agent timer_sw_agent_write write 1 STD_LOGIC Input
add_instantiation_interface_port timer_sw_agent timer_sw_agent_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port timer_sw_agent timer_sw_agent_byteenable byteenable 4 STD_LOGIC_VECTOR Input
add_instantiation_interface_port timer_sw_agent timer_sw_agent_address address 6 STD_LOGIC_VECTOR Input
add_instantiation_interface_port timer_sw_agent timer_sw_agent_read read 1 STD_LOGIC Input
add_instantiation_interface_port timer_sw_agent timer_sw_agent_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port timer_sw_agent timer_sw_agent_readdatavalid readdatavalid 1 STD_LOGIC Output
add_instantiation_interface dm_agent avalon INPUT
set_instantiation_interface_parameter_value dm_agent addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value dm_agent addressGroup {0}
set_instantiation_interface_parameter_value dm_agent addressSpan {65536}
set_instantiation_interface_parameter_value dm_agent addressUnits {SYMBOLS}
set_instantiation_interface_parameter_value dm_agent alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value dm_agent associatedClock {clk}
set_instantiation_interface_parameter_value dm_agent associatedReset {reset}
set_instantiation_interface_parameter_value dm_agent bitsPerSymbol {8}
set_instantiation_interface_parameter_value dm_agent bridgedAddressOffset {0}
set_instantiation_interface_parameter_value dm_agent bridgesToMaster {}
set_instantiation_interface_parameter_value dm_agent burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value dm_agent burstcountUnits {WORDS}
set_instantiation_interface_parameter_value dm_agent constantBurstBehavior {false}
set_instantiation_interface_parameter_value dm_agent explicitAddressSpan {0}
set_instantiation_interface_parameter_value dm_agent holdTime {0}
set_instantiation_interface_parameter_value dm_agent interleaveBursts {false}
set_instantiation_interface_parameter_value dm_agent isBigEndian {false}
set_instantiation_interface_parameter_value dm_agent isFlash {false}
set_instantiation_interface_parameter_value dm_agent isMemoryDevice {false}
set_instantiation_interface_parameter_value dm_agent isNonVolatileStorage {false}
set_instantiation_interface_parameter_value dm_agent linewrapBursts {false}
set_instantiation_interface_parameter_value dm_agent maximumPendingReadTransactions {2}
set_instantiation_interface_parameter_value dm_agent maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value dm_agent minimumReadLatency {1}
set_instantiation_interface_parameter_value dm_agent minimumResponseLatency {1}
set_instantiation_interface_parameter_value dm_agent minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value dm_agent prSafe {false}
set_instantiation_interface_parameter_value dm_agent printableDevice {false}
set_instantiation_interface_parameter_value dm_agent readLatency {0}
set_instantiation_interface_parameter_value dm_agent readWaitStates {1}
set_instantiation_interface_parameter_value dm_agent readWaitTime {1}
set_instantiation_interface_parameter_value dm_agent registerIncomingSignals {false}
set_instantiation_interface_parameter_value dm_agent registerOutgoingSignals {false}
set_instantiation_interface_parameter_value dm_agent setupTime {0}
set_instantiation_interface_parameter_value dm_agent timingUnits {Cycles}
set_instantiation_interface_parameter_value dm_agent transparentBridge {false}
set_instantiation_interface_parameter_value dm_agent waitrequestAllowance {0}
set_instantiation_interface_parameter_value dm_agent wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value dm_agent writeLatency {0}
set_instantiation_interface_parameter_value dm_agent writeWaitStates {0}
set_instantiation_interface_parameter_value dm_agent writeWaitTime {0}
set_instantiation_interface_assignment_value dm_agent embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value dm_agent embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value dm_agent embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value dm_agent embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_assignment_value dm_agent qsys.ui.connect {instruction_manager,data_manager}
set_instantiation_interface_sysinfo_parameter_value dm_agent address_map {<address-map><slave name='dm_agent' start='0x0' end='0x10000' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value dm_agent address_width {16}
set_instantiation_interface_sysinfo_parameter_value dm_agent max_slave_data_width {32}
add_instantiation_interface_port dm_agent dm_agent_write write 1 STD_LOGIC Input
add_instantiation_interface_port dm_agent dm_agent_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port dm_agent dm_agent_address address 16 STD_LOGIC_VECTOR Input
add_instantiation_interface_port dm_agent dm_agent_read read 1 STD_LOGIC Input
add_instantiation_interface_port dm_agent dm_agent_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port dm_agent dm_agent_readdatavalid readdatavalid 1 STD_LOGIC Output
add_instantiation_interface_port dm_agent dm_agent_waitrequest waitrequest 1 STD_LOGIC Output
add_instantiation_interface dbg_reset reset OUTPUT
set_instantiation_interface_parameter_value dbg_reset associatedClock {clk}
set_instantiation_interface_parameter_value dbg_reset associatedDirectReset {}
set_instantiation_interface_parameter_value dbg_reset associatedResetSinks {none}
set_instantiation_interface_parameter_value dbg_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port dbg_reset dbg_reset_reset reset 1 STD_LOGIC Output
save_instantiation
add_component sys_cpu_ram ip/sys/sys_cpu_ram.ip intel_onchip_memory sys_cpu_ram 1.3.0
load_component sys_cpu_ram
set_component_parameter_value AXI_interface {1}
set_component_parameter_value allowInSystemMemoryContentEditor {0}
set_component_parameter_value blockType {AUTO}
set_component_parameter_value clockEnable {0}
set_component_parameter_value copyInitFile {0}
set_component_parameter_value dataWidth {32}
set_component_parameter_value dataWidth2 {32}
set_component_parameter_value dualPort {0}
set_component_parameter_value enPRInitMode {0}
set_component_parameter_value enableDiffWidth {0}
set_component_parameter_value gui_debugaccess {0}
set_component_parameter_value idWidth {1}
set_component_parameter_value initMemContent {1}
set_component_parameter_value initializationFileName {software/app/build/app.hex}
set_component_parameter_value instanceID {NONE}
set_component_parameter_value interfaceType {0}
set_component_parameter_value lvl1OutputRegA {0}
set_component_parameter_value lvl1OutputRegB {0}
set_component_parameter_value lvl2OutputRegA {0}
set_component_parameter_value lvl2OutputRegB {0}
set_component_parameter_value memorySize {2000000.0}
set_component_parameter_value readDuringWriteMode_Mixed {DONT_CARE}
set_component_parameter_value resetrequest_enabled {1}
set_component_parameter_value singleClockOperation {0}
set_component_parameter_value tightly_coupled_ecc {0}
set_component_parameter_value useNonDefaultInitFile {1}
set_component_parameter_value writable {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_cpu_ram
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR {0}
set_instantiation_assignment_value embeddedsw.CMacro.CONTENTS_INFO {""}
set_instantiation_assignment_value embeddedsw.CMacro.DUAL_PORT {0}
set_instantiation_assignment_value embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE {AUTO}
set_instantiation_assignment_value embeddedsw.CMacro.INIT_CONTENTS_FILE {app}
set_instantiation_assignment_value embeddedsw.CMacro.INIT_MEM_CONTENT {1}
set_instantiation_assignment_value embeddedsw.CMacro.INSTANCE_ID {NONE}
set_instantiation_assignment_value embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED {1}
set_instantiation_assignment_value embeddedsw.CMacro.RAM_BLOCK_TYPE {AUTO}
set_instantiation_assignment_value embeddedsw.CMacro.READ_DURING_WRITE_MODE {DONT_CARE}
set_instantiation_assignment_value embeddedsw.CMacro.SINGLE_CLOCK_OP {0}
set_instantiation_assignment_value embeddedsw.CMacro.SIZE_MULTIPLE {1}
set_instantiation_assignment_value embeddedsw.CMacro.SIZE_VALUE {2000000}
set_instantiation_assignment_value embeddedsw.CMacro.WRITABLE {1}
set_instantiation_assignment_value embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR {SIM_DIR}
set_instantiation_assignment_value embeddedsw.memoryInfo.GENERATE_DAT_SYM {1}
set_instantiation_assignment_value embeddedsw.memoryInfo.GENERATE_HEX {1}
set_instantiation_assignment_value embeddedsw.memoryInfo.HAS_BYTE_LANE {0}
set_instantiation_assignment_value embeddedsw.memoryInfo.HEX_INSTALL_DIR {QPF_DIR}
set_instantiation_assignment_value embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH {32}
set_instantiation_assignment_value embeddedsw.memoryInfo.MEM_INIT_FILENAME {app}
set_instantiation_assignment_value postgeneration.simulation.init_file.param_name {INIT_FILE}
set_instantiation_assignment_value postgeneration.simulation.init_file.type {MEM_INIT}
add_instantiation_interface clk1 clock INPUT
set_instantiation_interface_parameter_value clk1 clockRate {0}
set_instantiation_interface_parameter_value clk1 externallyDriven {false}
set_instantiation_interface_parameter_value clk1 ptfSchematicName {}
add_instantiation_interface_port clk1 clk clk 1 STD_LOGIC Input
add_instantiation_interface s1 avalon INPUT
set_instantiation_interface_parameter_value s1 addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value s1 addressGroup {0}
set_instantiation_interface_parameter_value s1 addressSpan {2000000}
set_instantiation_interface_parameter_value s1 addressUnits {WORDS}
set_instantiation_interface_parameter_value s1 alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value s1 associatedClock {clk1}
set_instantiation_interface_parameter_value s1 associatedReset {reset1}
set_instantiation_interface_parameter_value s1 bitsPerSymbol {8}
set_instantiation_interface_parameter_value s1 bridgedAddressOffset {0}
set_instantiation_interface_parameter_value s1 bridgesToMaster {}
set_instantiation_interface_parameter_value s1 burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value s1 burstcountUnits {WORDS}
set_instantiation_interface_parameter_value s1 constantBurstBehavior {false}
set_instantiation_interface_parameter_value s1 explicitAddressSpan {2000000}
set_instantiation_interface_parameter_value s1 holdTime {0}
set_instantiation_interface_parameter_value s1 interleaveBursts {false}
set_instantiation_interface_parameter_value s1 isBigEndian {false}
set_instantiation_interface_parameter_value s1 isFlash {false}
set_instantiation_interface_parameter_value s1 isMemoryDevice {true}
set_instantiation_interface_parameter_value s1 isNonVolatileStorage {false}
set_instantiation_interface_parameter_value s1 linewrapBursts {false}
set_instantiation_interface_parameter_value s1 maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value s1 maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value s1 minimumReadLatency {1}
set_instantiation_interface_parameter_value s1 minimumResponseLatency {1}
set_instantiation_interface_parameter_value s1 minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value s1 prSafe {false}
set_instantiation_interface_parameter_value s1 printableDevice {false}
set_instantiation_interface_parameter_value s1 readLatency {1}
set_instantiation_interface_parameter_value s1 readWaitStates {0}
set_instantiation_interface_parameter_value s1 readWaitTime {0}
set_instantiation_interface_parameter_value s1 registerIncomingSignals {false}
set_instantiation_interface_parameter_value s1 registerOutgoingSignals {false}
set_instantiation_interface_parameter_value s1 setupTime {0}
set_instantiation_interface_parameter_value s1 timingUnits {Cycles}
set_instantiation_interface_parameter_value s1 transparentBridge {false}
set_instantiation_interface_parameter_value s1 waitrequestAllowance {0}
set_instantiation_interface_parameter_value s1 wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value s1 writeLatency {0}
set_instantiation_interface_parameter_value s1 writeWaitStates {0}
set_instantiation_interface_parameter_value s1 writeWaitTime {0}
set_instantiation_interface_assignment_value s1 embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value s1 embeddedsw.configuration.isMemoryDevice {1}
set_instantiation_interface_assignment_value s1 embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value s1 embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value s1 address_map {<address-map><slave name='s1' start='0x0' end='0x1E8480' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value s1 address_width {21}
set_instantiation_interface_sysinfo_parameter_value s1 max_slave_data_width {32}
add_instantiation_interface_port s1 address address 19 STD_LOGIC_VECTOR Input
add_instantiation_interface_port s1 read read 1 STD_LOGIC Input
add_instantiation_interface_port s1 readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port s1 byteenable byteenable 4 STD_LOGIC_VECTOR Input
add_instantiation_interface_port s1 write write 1 STD_LOGIC Input
add_instantiation_interface_port s1 writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface reset1 reset INPUT
set_instantiation_interface_parameter_value reset1 associatedClock {clk1}
set_instantiation_interface_parameter_value reset1 synchronousEdges {DEASSERT}
add_instantiation_interface_port reset1 reset reset 1 STD_LOGIC Input
add_instantiation_interface_port reset1 reset_req reset_req 1 STD_LOGIC Input
save_instantiation
add_component sys_e_tile ip/sys/sys_alt_ehipc3_fm_0.ip alt_ehipc3_fm alt_ehipc3_fm_0 21.0.0
load_component sys_e_tile
set_component_parameter_value AIB_test_sl {0}
set_component_parameter_value AN_CHAN {0}
set_component_parameter_value AN_PAUSE_C0 {1}
set_component_parameter_value AN_PAUSE_C1 {1}
set_component_parameter_value AVMM_test {0}
set_component_parameter_value AVMM_test_sl {0}
set_component_parameter_value CR_MODE {1}
set_component_parameter_value DEV_BOARD {0}
set_component_parameter_value EHIP_LOCATION {0}
set_component_parameter_value ENABLE_ADME {1}
set_component_parameter_value ENABLE_ADME_PTP_CHANNEL {0}
set_component_parameter_value ENABLE_AN {1}
set_component_parameter_value ENABLE_ANLT {0}
set_component_parameter_value ENABLE_ASYNC_ADAPTERS {0}
set_component_parameter_value ENABLE_ASYNC_ADAPTERS_SL {0}
set_component_parameter_value ENABLE_JTAG_AVMM {0}
set_component_parameter_value ENABLE_LT {1}
set_component_parameter_value ENABLE_PPM_TODSYNC {1}
set_component_parameter_value ENABLE_PTP {0}
set_component_parameter_value ENABLE_PTP_PPM {0}
set_component_parameter_value ENABLE_PTP_RX_DESKEW {1}
set_component_parameter_value ENABLE_PTP_TOG {0}
set_component_parameter_value ENABLE_RSFEC {1}
set_component_parameter_value ENABLE_SYNCE {0}
set_component_parameter_value ENHANCED_PTP_ACCURACY {0}
set_component_parameter_value ENHANCED_PTP_DBG {0}
set_component_parameter_value EN_DYN_FEC {0}
set_component_parameter_value EXAMPLE_DESIGN {1}
set_component_parameter_value GEN_SIM {1}
set_component_parameter_value GEN_SYNTH {1}
set_component_parameter_value HDL_FORMAT {1}
set_component_parameter_value LINK_TIMER_KR {504}
set_component_parameter_value PHY_REFCLK {156.250000}
set_component_parameter_value PHY_REFCLK_sl_0 {156.250000}
set_component_parameter_value PPM_VALUE_RX {0}
set_component_parameter_value PPM_VALUE_TX {0}
set_component_parameter_value RECONFIG_1025 {0}
set_component_parameter_value REQUEST_RSFEC {1}
set_component_parameter_value RSFEC_CLOCKING_MODE {fec_dir_adp_clk_0}
set_component_parameter_value RSFEC_FIRST_LANE_SEL {first_lane0}
set_component_parameter_value SL_OPT {2}
set_component_parameter_value STATUS_CLK_MHZ {100.0}
set_component_parameter_value USE_PTP_PLLCH {1}
set_component_parameter_value XCVR_test {0}
set_component_parameter_value active_channel {0}
set_component_parameter_value additional_ipg_removed {0}
set_component_parameter_value additional_ipg_removed_sl_0 {0}
set_component_parameter_value adpt_multi_enable {1}
set_component_parameter_value adpt_recipe_cnt {1}
set_component_parameter_value adpt_recipe_data0 {}
set_component_parameter_value adpt_recipe_data1 {}
set_component_parameter_value adpt_recipe_data2 {}
set_component_parameter_value adpt_recipe_data3 {}
set_component_parameter_value adpt_recipe_data4 {}
set_component_parameter_value adpt_recipe_data5 {}
set_component_parameter_value adpt_recipe_data6 {}
set_component_parameter_value adpt_recipe_data7 {}
set_component_parameter_value adpt_recipe_select {0}
set_component_parameter_value cal_recipe_sel {NRZ_28Gbps_VSR}
set_component_parameter_value core_variant {2}
set_component_parameter_value cpri_ehip_rate_gui {2}
set_component_parameter_value cpri_enable_custom_sl_0 {1}
set_component_parameter_value cpri_include_alternate_ports {0}
set_component_parameter_value cpri_include_refclk_mux_sl_0 {0}
set_component_parameter_value cpri_number_of_channel {1}
set_component_parameter_value ctle_gs1_val_a {999}
set_component_parameter_value ctle_gs1_val_b {999}
set_component_parameter_value ctle_gs2_val_a {999}
set_component_parameter_value ctle_gs2_val_b {999}
set_component_parameter_value ctle_hf_max_a {999}
set_component_parameter_value ctle_hf_max_b {999}
set_component_parameter_value ctle_hf_min_a {999}
set_component_parameter_value ctle_hf_min_b {999}
set_component_parameter_value ctle_hf_val_a {999}
set_component_parameter_value ctle_hf_val_ada_a {adaptable}
set_component_parameter_value ctle_hf_val_ada_b {adaptable}
set_component_parameter_value ctle_hf_val_b {999}
set_component_parameter_value ctle_lf_max_a {999}
set_component_parameter_value ctle_lf_max_b {999}
set_component_parameter_value ctle_lf_min_a {999}
set_component_parameter_value ctle_lf_min_b {999}
set_component_parameter_value ctle_lf_val_a {999}
set_component_parameter_value ctle_lf_val_ada_a {adaptable}
set_component_parameter_value ctle_lf_val_ada_b {adaptable}
set_component_parameter_value ctle_lf_val_b {999}
set_component_parameter_value custom_pcs_PHY_REFCLK {250.000000}
set_component_parameter_value custom_pcs_ehip_mode_gui {PCS_Only}
set_component_parameter_value custom_pcs_ehip_rate_gui {25000}
set_component_parameter_value custom_pcs_enable_custom {1}
set_component_parameter_value custom_pcs_fibre_channel_mode {disable}
set_component_parameter_value custom_pcs_include_alternate_ports {0}
set_component_parameter_value custom_pcs_modulation {NRZ}
set_component_parameter_value custom_pcs_number_of_channel {1}
set_component_parameter_value design_environment {QSYS}
set_component_parameter_value dis_anlt_std_recipe {0}
set_component_parameter_value disable_internal_dr {0}
set_component_parameter_value dr_100g_nrz_pam4 {0}
set_component_parameter_value dr_25g_cpri {0}
set_component_parameter_value duplex_mode {enable}
set_component_parameter_value ehip_mode_gui {MAC+PCS+(528,514)RSFEC}
set_component_parameter_value ehip_mode_gui_sl_0 {MAC+PCS+RSFEC}
set_component_parameter_value ehip_rate_gui {100G}
set_component_parameter_value ehip_rate_gui_sl_0 {25G}
set_component_parameter_value enable_aib_latency_adj_ena_ports {0}
set_component_parameter_value enable_custom_sl_0 {0}
set_component_parameter_value enable_external_aib_clocking {0}
set_component_parameter_value enable_internal_options {0}
set_component_parameter_value enable_rsfec_rst_ports {0}
set_component_parameter_value enforce_max_frame_size_gui {0}
set_component_parameter_value enforce_max_frame_size_gui_sl_0 {0}
set_component_parameter_value flow_control_gui {No}
set_component_parameter_value flow_control_gui_sl_0 {No}
set_component_parameter_value forward_rx_pause_requests_gui {0}
set_component_parameter_value forward_rx_pause_requests_gui_sl_0 {0}
set_component_parameter_value include_alternate_ports_sl_0 {0}
set_component_parameter_value include_dlat_sl_0 {0}
set_component_parameter_value include_refclk_mux_sl_0 {0}
set_component_parameter_value link_fault_mode_gui {Bidirectional}
set_component_parameter_value link_fault_mode_gui_sl_0 {Bidirectional}
set_component_parameter_value number_of_channel {0}
set_component_parameter_value preamble_passthrough_gui {0}
set_component_parameter_value preamble_passthrough_gui_sl_0 {0}
set_component_parameter_value preserve_unused_xcvr_channels {0}
set_component_parameter_value rcp_load_enable {0}
set_component_parameter_value ready_latency {0}
set_component_parameter_value ready_latency_sl {0}
set_component_parameter_value rf_a_a {999}
set_component_parameter_value rf_a_b {999}
set_component_parameter_value rf_b0_a {999}
set_component_parameter_value rf_b0_ada_a {adaptable}
set_component_parameter_value rf_b0_ada_b {adaptable}
set_component_parameter_value rf_b0_b {999}
set_component_parameter_value rf_b0t_a {999}
set_component_parameter_value rf_b0t_b {999}
set_component_parameter_value rf_b1_a {999}
set_component_parameter_value rf_b1_ada_a {adaptable}
set_component_parameter_value rf_b1_ada_b {adaptable}
set_component_parameter_value rf_b1_b {999}
set_component_parameter_value rf_p0_val_a {999}
set_component_parameter_value rf_p0_val_ada_a {adaptable}
set_component_parameter_value rf_p0_val_ada_b {adaptable}
set_component_parameter_value rf_p0_val_b {999}
set_component_parameter_value rf_p1_max_a {999}
set_component_parameter_value rf_p1_max_b {999}
set_component_parameter_value rf_p1_min_a {999}
set_component_parameter_value rf_p1_min_b {999}
set_component_parameter_value rf_p1_val_a {999}
set_component_parameter_value rf_p1_val_ada_a {adaptable}
set_component_parameter_value rf_p1_val_ada_b {adaptable}
set_component_parameter_value rf_p1_val_b {999}
set_component_parameter_value rf_p2_max_a {999}
set_component_parameter_value rf_p2_max_b {999}
set_component_parameter_value rf_p2_min_a {999}
set_component_parameter_value rf_p2_min_b {999}
set_component_parameter_value rf_p2_val_a {999}
set_component_parameter_value rf_p2_val_ada_a {adaptable}
set_component_parameter_value rf_p2_val_ada_b {adaptable}
set_component_parameter_value rf_p2_val_b {999}
set_component_parameter_value rf_reserved0_a {999}
set_component_parameter_value rf_reserved0_b {999}
set_component_parameter_value rf_reserved1_a {999}
set_component_parameter_value rf_reserved1_b {999}
set_component_parameter_value rx_bytes_to_remove {Remove CRC bytes}
set_component_parameter_value rx_bytes_to_remove_sl_0 {Remove CRC bytes}
set_component_parameter_value rx_max_frame_size_gui {1518}
set_component_parameter_value rx_max_frame_size_gui_sl_0 {1518}
set_component_parameter_value rx_vlan_detection_gui {1}
set_component_parameter_value rx_vlan_detection_gui_sl_0 {1}
set_component_parameter_value source_address_insertion_gui {0}
set_component_parameter_value source_address_insertion_gui_sl_0 {0}
set_component_parameter_value strict_preamble_checking_gui {0}
set_component_parameter_value strict_preamble_checking_gui_sl_0 {0}
set_component_parameter_value strict_sfd_checking_gui {0}
set_component_parameter_value strict_sfd_checking_gui_sl_0 {0}
set_component_parameter_value tx_ipg_size_gui {12}
set_component_parameter_value tx_ipg_size_gui_sl_0 {12}
set_component_parameter_value tx_max_frame_size_gui {1518}
set_component_parameter_value tx_max_frame_size_gui_sl_0 {1518}
set_component_parameter_value tx_vlan_detection_gui {1}
set_component_parameter_value tx_vlan_detection_gui_sl_0 {1}
set_component_parameter_value txmac_saddr_gui {73588229205}
set_component_parameter_value user_bti_refclk_freq_mhz {156.250000}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_e_tile
remove_instantiation_interfaces_and_ports
add_instantiation_interface i_stats_snapshot conduit INPUT
set_instantiation_interface_parameter_value i_stats_snapshot associatedClock {}
set_instantiation_interface_parameter_value i_stats_snapshot associatedReset {}
set_instantiation_interface_parameter_value i_stats_snapshot prSafe {false}
add_instantiation_interface_port i_stats_snapshot i_stats_snapshot i_stats_snapshot 1 STD_LOGIC Input
add_instantiation_interface o_cdr_lock conduit INPUT
set_instantiation_interface_parameter_value o_cdr_lock associatedClock {}
set_instantiation_interface_parameter_value o_cdr_lock associatedReset {}
set_instantiation_interface_parameter_value o_cdr_lock prSafe {false}
add_instantiation_interface_port o_cdr_lock o_cdr_lock o_cdr_lock 1 STD_LOGIC_VECTOR Output
add_instantiation_interface o_tx_pll_locked conduit INPUT
set_instantiation_interface_parameter_value o_tx_pll_locked associatedClock {}
set_instantiation_interface_parameter_value o_tx_pll_locked associatedReset {}
set_instantiation_interface_parameter_value o_tx_pll_locked prSafe {false}
add_instantiation_interface_port o_tx_pll_locked o_tx_pll_locked o_tx_pll_locked 1 STD_LOGIC_VECTOR Output
add_instantiation_interface eth_reconfig avalon INPUT
set_instantiation_interface_parameter_value eth_reconfig addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value eth_reconfig addressGroup {0}
set_instantiation_interface_parameter_value eth_reconfig addressSpan {8388608}
set_instantiation_interface_parameter_value eth_reconfig addressUnits {WORDS}
set_instantiation_interface_parameter_value eth_reconfig alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value eth_reconfig associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value eth_reconfig associatedReset {i_reconfig_reset}
set_instantiation_interface_parameter_value eth_reconfig bitsPerSymbol {8}
set_instantiation_interface_parameter_value eth_reconfig bridgedAddressOffset {0}
set_instantiation_interface_parameter_value eth_reconfig bridgesToMaster {}
set_instantiation_interface_parameter_value eth_reconfig burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value eth_reconfig burstcountUnits {WORDS}
set_instantiation_interface_parameter_value eth_reconfig constantBurstBehavior {false}
set_instantiation_interface_parameter_value eth_reconfig explicitAddressSpan {0}
set_instantiation_interface_parameter_value eth_reconfig holdTime {0}
set_instantiation_interface_parameter_value eth_reconfig interleaveBursts {false}
set_instantiation_interface_parameter_value eth_reconfig isBigEndian {false}
set_instantiation_interface_parameter_value eth_reconfig isFlash {false}
set_instantiation_interface_parameter_value eth_reconfig isMemoryDevice {false}
set_instantiation_interface_parameter_value eth_reconfig isNonVolatileStorage {false}
set_instantiation_interface_parameter_value eth_reconfig linewrapBursts {false}
set_instantiation_interface_parameter_value eth_reconfig maximumPendingReadTransactions {1}
set_instantiation_interface_parameter_value eth_reconfig maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value eth_reconfig minimumReadLatency {1}
set_instantiation_interface_parameter_value eth_reconfig minimumResponseLatency {1}
set_instantiation_interface_parameter_value eth_reconfig minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value eth_reconfig prSafe {false}
set_instantiation_interface_parameter_value eth_reconfig printableDevice {false}
set_instantiation_interface_parameter_value eth_reconfig readLatency {0}
set_instantiation_interface_parameter_value eth_reconfig readWaitStates {1}
set_instantiation_interface_parameter_value eth_reconfig readWaitTime {1}
set_instantiation_interface_parameter_value eth_reconfig registerIncomingSignals {false}
set_instantiation_interface_parameter_value eth_reconfig registerOutgoingSignals {false}
set_instantiation_interface_parameter_value eth_reconfig setupTime {0}
set_instantiation_interface_parameter_value eth_reconfig timingUnits {Cycles}
set_instantiation_interface_parameter_value eth_reconfig transparentBridge {false}
set_instantiation_interface_parameter_value eth_reconfig waitrequestAllowance {0}
set_instantiation_interface_parameter_value eth_reconfig wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value eth_reconfig writeLatency {0}
set_instantiation_interface_parameter_value eth_reconfig writeWaitStates {0}
set_instantiation_interface_parameter_value eth_reconfig writeWaitTime {0}
set_instantiation_interface_assignment_value eth_reconfig embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value eth_reconfig embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value eth_reconfig embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value eth_reconfig embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value eth_reconfig address_map {<address-map><slave name='eth_reconfig' start='0x0' end='0x800000' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value eth_reconfig address_width {23}
set_instantiation_interface_sysinfo_parameter_value eth_reconfig max_slave_data_width {32}
add_instantiation_interface_port eth_reconfig i_eth_reconfig_addr address 21 STD_LOGIC_VECTOR Input
add_instantiation_interface_port eth_reconfig i_eth_reconfig_read read 1 STD_LOGIC Input
add_instantiation_interface_port eth_reconfig i_eth_reconfig_write write 1 STD_LOGIC Input
add_instantiation_interface_port eth_reconfig o_eth_reconfig_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port eth_reconfig o_eth_reconfig_readdata_valid readdatavalid 1 STD_LOGIC Output
add_instantiation_interface_port eth_reconfig i_eth_reconfig_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port eth_reconfig o_eth_reconfig_waitrequest waitrequest 1 STD_LOGIC Output
add_instantiation_interface rsfec_reconfig avalon INPUT
set_instantiation_interface_parameter_value rsfec_reconfig addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value rsfec_reconfig addressGroup {0}
set_instantiation_interface_parameter_value rsfec_reconfig addressSpan {2048}
set_instantiation_interface_parameter_value rsfec_reconfig addressUnits {WORDS}
set_instantiation_interface_parameter_value rsfec_reconfig alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value rsfec_reconfig associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value rsfec_reconfig associatedReset {i_reconfig_reset}
set_instantiation_interface_parameter_value rsfec_reconfig bitsPerSymbol {8}
set_instantiation_interface_parameter_value rsfec_reconfig bridgedAddressOffset {0}
set_instantiation_interface_parameter_value rsfec_reconfig bridgesToMaster {}
set_instantiation_interface_parameter_value rsfec_reconfig burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value rsfec_reconfig burstcountUnits {WORDS}
set_instantiation_interface_parameter_value rsfec_reconfig constantBurstBehavior {false}
set_instantiation_interface_parameter_value rsfec_reconfig explicitAddressSpan {0}
set_instantiation_interface_parameter_value rsfec_reconfig holdTime {0}
set_instantiation_interface_parameter_value rsfec_reconfig interleaveBursts {false}
set_instantiation_interface_parameter_value rsfec_reconfig isBigEndian {false}
set_instantiation_interface_parameter_value rsfec_reconfig isFlash {false}
set_instantiation_interface_parameter_value rsfec_reconfig isMemoryDevice {false}
set_instantiation_interface_parameter_value rsfec_reconfig isNonVolatileStorage {false}
set_instantiation_interface_parameter_value rsfec_reconfig linewrapBursts {false}
set_instantiation_interface_parameter_value rsfec_reconfig maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value rsfec_reconfig maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value rsfec_reconfig minimumReadLatency {1}
set_instantiation_interface_parameter_value rsfec_reconfig minimumResponseLatency {1}
set_instantiation_interface_parameter_value rsfec_reconfig minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value rsfec_reconfig prSafe {false}
set_instantiation_interface_parameter_value rsfec_reconfig printableDevice {false}
set_instantiation_interface_parameter_value rsfec_reconfig readLatency {0}
set_instantiation_interface_parameter_value rsfec_reconfig readWaitStates {1}
set_instantiation_interface_parameter_value rsfec_reconfig readWaitTime {1}
set_instantiation_interface_parameter_value rsfec_reconfig registerIncomingSignals {false}
set_instantiation_interface_parameter_value rsfec_reconfig registerOutgoingSignals {false}
set_instantiation_interface_parameter_value rsfec_reconfig setupTime {0}
set_instantiation_interface_parameter_value rsfec_reconfig timingUnits {Cycles}
set_instantiation_interface_parameter_value rsfec_reconfig transparentBridge {false}
set_instantiation_interface_parameter_value rsfec_reconfig waitrequestAllowance {0}
set_instantiation_interface_parameter_value rsfec_reconfig wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value rsfec_reconfig writeLatency {0}
set_instantiation_interface_parameter_value rsfec_reconfig writeWaitStates {0}
set_instantiation_interface_parameter_value rsfec_reconfig writeWaitTime {0}
set_instantiation_interface_assignment_value rsfec_reconfig embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value rsfec_reconfig embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value rsfec_reconfig embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value rsfec_reconfig embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value rsfec_reconfig address_map {<address-map><slave name='rsfec_reconfig' start='0x0' end='0x800' datawidth='8' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value rsfec_reconfig address_width {11}
set_instantiation_interface_sysinfo_parameter_value rsfec_reconfig max_slave_data_width {8}
add_instantiation_interface_port rsfec_reconfig i_rsfec_reconfig_addr address 11 STD_LOGIC_VECTOR Input
add_instantiation_interface_port rsfec_reconfig i_rsfec_reconfig_read read 1 STD_LOGIC Input
add_instantiation_interface_port rsfec_reconfig i_rsfec_reconfig_write write 1 STD_LOGIC Input
add_instantiation_interface_port rsfec_reconfig o_rsfec_reconfig_readdata readdata 8 STD_LOGIC_VECTOR Output
add_instantiation_interface_port rsfec_reconfig i_rsfec_reconfig_writedata writedata 8 STD_LOGIC_VECTOR Input
add_instantiation_interface_port rsfec_reconfig o_rsfec_reconfig_waitrequest waitrequest 1 STD_LOGIC Output
add_instantiation_interface o_tx_lanes_stable conduit INPUT
set_instantiation_interface_parameter_value o_tx_lanes_stable associatedClock {}
set_instantiation_interface_parameter_value o_tx_lanes_stable associatedReset {}
set_instantiation_interface_parameter_value o_tx_lanes_stable prSafe {false}
add_instantiation_interface_port o_tx_lanes_stable o_tx_lanes_stable o_tx_lanes_stable 1 STD_LOGIC Output
add_instantiation_interface o_rx_pcs_ready conduit INPUT
set_instantiation_interface_parameter_value o_rx_pcs_ready associatedClock {}
set_instantiation_interface_parameter_value o_rx_pcs_ready associatedReset {}
set_instantiation_interface_parameter_value o_rx_pcs_ready prSafe {false}
add_instantiation_interface_port o_rx_pcs_ready o_rx_pcs_ready o_rx_pcs_ready 1 STD_LOGIC Output
add_instantiation_interface o_ehip_ready conduit INPUT
set_instantiation_interface_parameter_value o_ehip_ready associatedClock {}
set_instantiation_interface_parameter_value o_ehip_ready associatedReset {}
set_instantiation_interface_parameter_value o_ehip_ready prSafe {false}
add_instantiation_interface_port o_ehip_ready o_ehip_ready o_ehip_ready 1 STD_LOGIC Output
add_instantiation_interface o_rx_block_lock conduit INPUT
set_instantiation_interface_parameter_value o_rx_block_lock associatedClock {}
set_instantiation_interface_parameter_value o_rx_block_lock associatedReset {}
set_instantiation_interface_parameter_value o_rx_block_lock prSafe {false}
add_instantiation_interface_port o_rx_block_lock o_rx_block_lock o_rx_block_lock 1 STD_LOGIC Output
add_instantiation_interface o_rx_am_lock conduit INPUT
set_instantiation_interface_parameter_value o_rx_am_lock associatedClock {}
set_instantiation_interface_parameter_value o_rx_am_lock associatedReset {}
set_instantiation_interface_parameter_value o_rx_am_lock prSafe {false}
add_instantiation_interface_port o_rx_am_lock o_rx_am_lock o_rx_am_lock 1 STD_LOGIC Output
add_instantiation_interface o_rx_hi_ber conduit INPUT
set_instantiation_interface_parameter_value o_rx_hi_ber associatedClock {}
set_instantiation_interface_parameter_value o_rx_hi_ber associatedReset {}
set_instantiation_interface_parameter_value o_rx_hi_ber prSafe {false}
add_instantiation_interface_port o_rx_hi_ber o_rx_hi_ber o_rx_hi_ber 1 STD_LOGIC Output
add_instantiation_interface o_local_fault_status conduit INPUT
set_instantiation_interface_parameter_value o_local_fault_status associatedClock {}
set_instantiation_interface_parameter_value o_local_fault_status associatedReset {}
set_instantiation_interface_parameter_value o_local_fault_status prSafe {false}
add_instantiation_interface_port o_local_fault_status o_local_fault_status o_local_fault_status 1 STD_LOGIC Output
add_instantiation_interface o_remote_fault_status conduit INPUT
set_instantiation_interface_parameter_value o_remote_fault_status associatedClock {}
set_instantiation_interface_parameter_value o_remote_fault_status associatedReset {}
set_instantiation_interface_parameter_value o_remote_fault_status prSafe {false}
add_instantiation_interface_port o_remote_fault_status o_remote_fault_status o_remote_fault_status 1 STD_LOGIC Output
add_instantiation_interface i_clk_tx clock INPUT
set_instantiation_interface_parameter_value i_clk_tx clockRate {0}
set_instantiation_interface_parameter_value i_clk_tx externallyDriven {false}
set_instantiation_interface_parameter_value i_clk_tx ptfSchematicName {}
add_instantiation_interface_port i_clk_tx i_clk_tx clk 1 STD_LOGIC Input
add_instantiation_interface i_clk_rx clock INPUT
set_instantiation_interface_parameter_value i_clk_rx clockRate {0}
set_instantiation_interface_parameter_value i_clk_rx externallyDriven {false}
set_instantiation_interface_parameter_value i_clk_rx ptfSchematicName {}
add_instantiation_interface_port i_clk_rx i_clk_rx clk 1 STD_LOGIC Input
add_instantiation_interface i_csr_rst_n reset INPUT
set_instantiation_interface_parameter_value i_csr_rst_n associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value i_csr_rst_n synchronousEdges {DEASSERT}
add_instantiation_interface_port i_csr_rst_n i_csr_rst_n reset 1 STD_LOGIC Input
add_instantiation_interface i_tx_rst_n reset INPUT
set_instantiation_interface_parameter_value i_tx_rst_n associatedClock {i_clk_tx}
set_instantiation_interface_parameter_value i_tx_rst_n synchronousEdges {DEASSERT}
add_instantiation_interface_port i_tx_rst_n i_tx_rst_n reset 1 STD_LOGIC Input
add_instantiation_interface i_rx_rst_n reset INPUT
set_instantiation_interface_parameter_value i_rx_rst_n associatedClock {i_clk_rx}
set_instantiation_interface_parameter_value i_rx_rst_n synchronousEdges {DEASSERT}
add_instantiation_interface_port i_rx_rst_n i_rx_rst_n reset 1 STD_LOGIC Input
add_instantiation_interface serial_p conduit INPUT
set_instantiation_interface_parameter_value serial_p associatedClock {}
set_instantiation_interface_parameter_value serial_p associatedReset {}
set_instantiation_interface_parameter_value serial_p prSafe {false}
add_instantiation_interface_port serial_p o_tx_serial o_tx_serial 4 STD_LOGIC_VECTOR Output
add_instantiation_interface_port serial_p i_rx_serial i_rx_serial 4 STD_LOGIC_VECTOR Input
add_instantiation_interface serial_n conduit INPUT
set_instantiation_interface_parameter_value serial_n associatedClock {}
set_instantiation_interface_parameter_value serial_n associatedReset {}
set_instantiation_interface_parameter_value serial_n prSafe {false}
add_instantiation_interface_port serial_n o_tx_serial_n o_tx_serial_n 4 STD_LOGIC_VECTOR Output
add_instantiation_interface_port serial_n i_rx_serial_n i_rx_serial_n 4 STD_LOGIC_VECTOR Input
add_instantiation_interface i_reconfig_clk clock INPUT
set_instantiation_interface_parameter_value i_reconfig_clk clockRate {0}
set_instantiation_interface_parameter_value i_reconfig_clk externallyDriven {false}
set_instantiation_interface_parameter_value i_reconfig_clk ptfSchematicName {}
add_instantiation_interface_port i_reconfig_clk i_reconfig_clk clk 1 STD_LOGIC Input
add_instantiation_interface i_reconfig_reset reset INPUT
set_instantiation_interface_parameter_value i_reconfig_reset associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value i_reconfig_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port i_reconfig_reset i_reconfig_reset reset 1 STD_LOGIC Input
add_instantiation_interface tx_streaming avalon_streaming INPUT
set_instantiation_interface_parameter_value tx_streaming associatedClock {i_clk_tx}
set_instantiation_interface_parameter_value tx_streaming associatedReset {i_tx_rst_n}
set_instantiation_interface_parameter_value tx_streaming beatsPerCycle {1}
set_instantiation_interface_parameter_value tx_streaming dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value tx_streaming emptyWithinPacket {false}
set_instantiation_interface_parameter_value tx_streaming errorDescriptor {}
set_instantiation_interface_parameter_value tx_streaming firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value tx_streaming highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value tx_streaming maxChannel {0}
set_instantiation_interface_parameter_value tx_streaming packetDescription {}
set_instantiation_interface_parameter_value tx_streaming prSafe {false}
set_instantiation_interface_parameter_value tx_streaming readyAllowance {0}
set_instantiation_interface_parameter_value tx_streaming readyLatency {0}
set_instantiation_interface_parameter_value tx_streaming symbolsPerBeat {1}
add_instantiation_interface_port tx_streaming o_tx_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port tx_streaming i_tx_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port tx_streaming i_tx_data data 512 STD_LOGIC_VECTOR Input
add_instantiation_interface_port tx_streaming i_tx_error error 1 STD_LOGIC Input
add_instantiation_interface_port tx_streaming i_tx_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port tx_streaming i_tx_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port tx_streaming i_tx_empty empty 6 STD_LOGIC_VECTOR Input
add_instantiation_interface rx_streaming avalon_streaming OUTPUT
set_instantiation_interface_parameter_value rx_streaming associatedClock {i_clk_rx}
set_instantiation_interface_parameter_value rx_streaming associatedReset {i_rx_rst_n}
set_instantiation_interface_parameter_value rx_streaming beatsPerCycle {1}
set_instantiation_interface_parameter_value rx_streaming dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value rx_streaming emptyWithinPacket {false}
set_instantiation_interface_parameter_value rx_streaming errorDescriptor {}
set_instantiation_interface_parameter_value rx_streaming firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value rx_streaming highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value rx_streaming maxChannel {0}
set_instantiation_interface_parameter_value rx_streaming packetDescription {}
set_instantiation_interface_parameter_value rx_streaming prSafe {false}
set_instantiation_interface_parameter_value rx_streaming readyAllowance {0}
set_instantiation_interface_parameter_value rx_streaming readyLatency {0}
set_instantiation_interface_parameter_value rx_streaming symbolsPerBeat {1}
add_instantiation_interface_port rx_streaming o_rx_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port rx_streaming o_rx_data data 512 STD_LOGIC_VECTOR Output
add_instantiation_interface_port rx_streaming o_rx_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port rx_streaming o_rx_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port rx_streaming o_rx_empty empty 6 STD_LOGIC_VECTOR Output
add_instantiation_interface_port rx_streaming o_rx_error error 6 STD_LOGIC_VECTOR Output
add_instantiation_interface xcvr_reconfig_0 avalon INPUT
set_instantiation_interface_parameter_value xcvr_reconfig_0 addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value xcvr_reconfig_0 addressGroup {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 addressSpan {524288}
set_instantiation_interface_parameter_value xcvr_reconfig_0 addressUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_0 alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value xcvr_reconfig_0 associatedReset {i_reconfig_reset}
set_instantiation_interface_parameter_value xcvr_reconfig_0 bitsPerSymbol {8}
set_instantiation_interface_parameter_value xcvr_reconfig_0 bridgedAddressOffset {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 bridgesToMaster {}
set_instantiation_interface_parameter_value xcvr_reconfig_0 burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 burstcountUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_0 constantBurstBehavior {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 explicitAddressSpan {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 holdTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 interleaveBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 isBigEndian {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 isFlash {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 isMemoryDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 isNonVolatileStorage {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 linewrapBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 minimumReadLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_0 minimumResponseLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_0 minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value xcvr_reconfig_0 prSafe {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 printableDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 readLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 readWaitStates {1}
set_instantiation_interface_parameter_value xcvr_reconfig_0 readWaitTime {1}
set_instantiation_interface_parameter_value xcvr_reconfig_0 registerIncomingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 registerOutgoingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 setupTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 timingUnits {Cycles}
set_instantiation_interface_parameter_value xcvr_reconfig_0 transparentBridge {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 waitrequestAllowance {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value xcvr_reconfig_0 writeLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 writeWaitStates {0}
set_instantiation_interface_parameter_value xcvr_reconfig_0 writeWaitTime {0}
set_instantiation_interface_assignment_value xcvr_reconfig_0 embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value xcvr_reconfig_0 embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value xcvr_reconfig_0 embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value xcvr_reconfig_0 embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_0 address_map {<address-map><slave name='xcvr_reconfig_0' start='0x0' end='0x80000' datawidth='8' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_0 address_width {19}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_0 max_slave_data_width {8}
add_instantiation_interface_port xcvr_reconfig_0 i_xcvr_reconfig_address_0 address 19 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_0 i_xcvr_reconfig_read_0 read 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_0 i_xcvr_reconfig_write_0 write 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_0 o_xcvr_reconfig_readdata_0 readdata 8 STD_LOGIC_VECTOR Output
add_instantiation_interface_port xcvr_reconfig_0 i_xcvr_reconfig_writedata_0 writedata 8 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_0 o_xcvr_reconfig_waitrequest_0 waitrequest 1 STD_LOGIC Output
add_instantiation_interface xcvr_reconfig_1 avalon INPUT
set_instantiation_interface_parameter_value xcvr_reconfig_1 addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value xcvr_reconfig_1 addressGroup {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 addressSpan {524288}
set_instantiation_interface_parameter_value xcvr_reconfig_1 addressUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_1 alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value xcvr_reconfig_1 associatedReset {i_reconfig_reset}
set_instantiation_interface_parameter_value xcvr_reconfig_1 bitsPerSymbol {8}
set_instantiation_interface_parameter_value xcvr_reconfig_1 bridgedAddressOffset {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 bridgesToMaster {}
set_instantiation_interface_parameter_value xcvr_reconfig_1 burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 burstcountUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_1 constantBurstBehavior {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 explicitAddressSpan {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 holdTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 interleaveBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 isBigEndian {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 isFlash {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 isMemoryDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 isNonVolatileStorage {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 linewrapBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 minimumReadLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_1 minimumResponseLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_1 minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value xcvr_reconfig_1 prSafe {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 printableDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 readLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 readWaitStates {1}
set_instantiation_interface_parameter_value xcvr_reconfig_1 readWaitTime {1}
set_instantiation_interface_parameter_value xcvr_reconfig_1 registerIncomingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 registerOutgoingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 setupTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 timingUnits {Cycles}
set_instantiation_interface_parameter_value xcvr_reconfig_1 transparentBridge {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 waitrequestAllowance {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value xcvr_reconfig_1 writeLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 writeWaitStates {0}
set_instantiation_interface_parameter_value xcvr_reconfig_1 writeWaitTime {0}
set_instantiation_interface_assignment_value xcvr_reconfig_1 embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value xcvr_reconfig_1 embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value xcvr_reconfig_1 embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value xcvr_reconfig_1 embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_1 address_map {<address-map><slave name='xcvr_reconfig_1' start='0x0' end='0x80000' datawidth='8' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_1 address_width {19}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_1 max_slave_data_width {8}
add_instantiation_interface_port xcvr_reconfig_1 i_xcvr_reconfig_address_1 address 19 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_1 i_xcvr_reconfig_read_1 read 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_1 i_xcvr_reconfig_write_1 write 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_1 o_xcvr_reconfig_readdata_1 readdata 8 STD_LOGIC_VECTOR Output
add_instantiation_interface_port xcvr_reconfig_1 i_xcvr_reconfig_writedata_1 writedata 8 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_1 o_xcvr_reconfig_waitrequest_1 waitrequest 1 STD_LOGIC Output
add_instantiation_interface xcvr_reconfig_2 avalon INPUT
set_instantiation_interface_parameter_value xcvr_reconfig_2 addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value xcvr_reconfig_2 addressGroup {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 addressSpan {524288}
set_instantiation_interface_parameter_value xcvr_reconfig_2 addressUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_2 alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value xcvr_reconfig_2 associatedReset {i_reconfig_reset}
set_instantiation_interface_parameter_value xcvr_reconfig_2 bitsPerSymbol {8}
set_instantiation_interface_parameter_value xcvr_reconfig_2 bridgedAddressOffset {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 bridgesToMaster {}
set_instantiation_interface_parameter_value xcvr_reconfig_2 burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 burstcountUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_2 constantBurstBehavior {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 explicitAddressSpan {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 holdTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 interleaveBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 isBigEndian {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 isFlash {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 isMemoryDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 isNonVolatileStorage {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 linewrapBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 minimumReadLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_2 minimumResponseLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_2 minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value xcvr_reconfig_2 prSafe {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 printableDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 readLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 readWaitStates {1}
set_instantiation_interface_parameter_value xcvr_reconfig_2 readWaitTime {1}
set_instantiation_interface_parameter_value xcvr_reconfig_2 registerIncomingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 registerOutgoingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 setupTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 timingUnits {Cycles}
set_instantiation_interface_parameter_value xcvr_reconfig_2 transparentBridge {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 waitrequestAllowance {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value xcvr_reconfig_2 writeLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 writeWaitStates {0}
set_instantiation_interface_parameter_value xcvr_reconfig_2 writeWaitTime {0}
set_instantiation_interface_assignment_value xcvr_reconfig_2 embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value xcvr_reconfig_2 embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value xcvr_reconfig_2 embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value xcvr_reconfig_2 embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_2 address_map {<address-map><slave name='xcvr_reconfig_2' start='0x0' end='0x80000' datawidth='8' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_2 address_width {19}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_2 max_slave_data_width {8}
add_instantiation_interface_port xcvr_reconfig_2 i_xcvr_reconfig_address_2 address 19 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_2 i_xcvr_reconfig_read_2 read 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_2 i_xcvr_reconfig_write_2 write 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_2 o_xcvr_reconfig_readdata_2 readdata 8 STD_LOGIC_VECTOR Output
add_instantiation_interface_port xcvr_reconfig_2 i_xcvr_reconfig_writedata_2 writedata 8 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_2 o_xcvr_reconfig_waitrequest_2 waitrequest 1 STD_LOGIC Output
add_instantiation_interface xcvr_reconfig_3 avalon INPUT
set_instantiation_interface_parameter_value xcvr_reconfig_3 addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value xcvr_reconfig_3 addressGroup {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 addressSpan {524288}
set_instantiation_interface_parameter_value xcvr_reconfig_3 addressUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_3 alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 associatedClock {i_reconfig_clk}
set_instantiation_interface_parameter_value xcvr_reconfig_3 associatedReset {i_reconfig_reset}
set_instantiation_interface_parameter_value xcvr_reconfig_3 bitsPerSymbol {8}
set_instantiation_interface_parameter_value xcvr_reconfig_3 bridgedAddressOffset {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 bridgesToMaster {}
set_instantiation_interface_parameter_value xcvr_reconfig_3 burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 burstcountUnits {WORDS}
set_instantiation_interface_parameter_value xcvr_reconfig_3 constantBurstBehavior {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 explicitAddressSpan {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 holdTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 interleaveBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 isBigEndian {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 isFlash {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 isMemoryDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 isNonVolatileStorage {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 linewrapBursts {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 minimumReadLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_3 minimumResponseLatency {1}
set_instantiation_interface_parameter_value xcvr_reconfig_3 minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value xcvr_reconfig_3 prSafe {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 printableDevice {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 readLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 readWaitStates {1}
set_instantiation_interface_parameter_value xcvr_reconfig_3 readWaitTime {1}
set_instantiation_interface_parameter_value xcvr_reconfig_3 registerIncomingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 registerOutgoingSignals {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 setupTime {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 timingUnits {Cycles}
set_instantiation_interface_parameter_value xcvr_reconfig_3 transparentBridge {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 waitrequestAllowance {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value xcvr_reconfig_3 writeLatency {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 writeWaitStates {0}
set_instantiation_interface_parameter_value xcvr_reconfig_3 writeWaitTime {0}
set_instantiation_interface_assignment_value xcvr_reconfig_3 embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value xcvr_reconfig_3 embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value xcvr_reconfig_3 embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value xcvr_reconfig_3 embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_3 address_map {<address-map><slave name='xcvr_reconfig_3' start='0x0' end='0x80000' datawidth='8' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_3 address_width {19}
set_instantiation_interface_sysinfo_parameter_value xcvr_reconfig_3 max_slave_data_width {8}
add_instantiation_interface_port xcvr_reconfig_3 i_xcvr_reconfig_address_3 address 19 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_3 i_xcvr_reconfig_read_3 read 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_3 i_xcvr_reconfig_write_3 write 1 STD_LOGIC Input
add_instantiation_interface_port xcvr_reconfig_3 o_xcvr_reconfig_readdata_3 readdata 8 STD_LOGIC_VECTOR Output
add_instantiation_interface_port xcvr_reconfig_3 i_xcvr_reconfig_writedata_3 writedata 8 STD_LOGIC_VECTOR Input
add_instantiation_interface_port xcvr_reconfig_3 o_xcvr_reconfig_waitrequest_3 waitrequest 1 STD_LOGIC Output
add_instantiation_interface i_clk_ref_0 clock INPUT
set_instantiation_interface_parameter_value i_clk_ref_0 clockRate {0}
set_instantiation_interface_parameter_value i_clk_ref_0 externallyDriven {false}
set_instantiation_interface_parameter_value i_clk_ref_0 ptfSchematicName {}
add_instantiation_interface_port i_clk_ref_0 i_clk_ref_0 clk 1 STD_LOGIC Input
add_instantiation_interface o_clk_pll_div64_0 clock OUTPUT
set_instantiation_interface_parameter_value o_clk_pll_div64_0 associatedDirectClock {}
set_instantiation_interface_parameter_value o_clk_pll_div64_0 clockRate {0}
set_instantiation_interface_parameter_value o_clk_pll_div64_0 clockRateKnown {false}
set_instantiation_interface_parameter_value o_clk_pll_div64_0 externallyDriven {false}
set_instantiation_interface_parameter_value o_clk_pll_div64_0 ptfSchematicName {}
set_instantiation_interface_sysinfo_parameter_value o_clk_pll_div64_0 clock_rate {0}
add_instantiation_interface_port o_clk_pll_div64_0 o_clk_pll_div64_0 clk 1 STD_LOGIC Output
add_instantiation_interface o_clk_pll_div66_0 clock OUTPUT
set_instantiation_interface_parameter_value o_clk_pll_div66_0 associatedDirectClock {}
set_instantiation_interface_parameter_value o_clk_pll_div66_0 clockRate {0}
set_instantiation_interface_parameter_value o_clk_pll_div66_0 clockRateKnown {false}
set_instantiation_interface_parameter_value o_clk_pll_div66_0 externallyDriven {false}
set_instantiation_interface_parameter_value o_clk_pll_div66_0 ptfSchematicName {}
set_instantiation_interface_sysinfo_parameter_value o_clk_pll_div66_0 clock_rate {0}
add_instantiation_interface_port o_clk_pll_div66_0 o_clk_pll_div66_0 clk 1 STD_LOGIC Output
add_instantiation_interface o_clk_rec_div64_0 clock OUTPUT
set_instantiation_interface_parameter_value o_clk_rec_div64_0 associatedDirectClock {}
set_instantiation_interface_parameter_value o_clk_rec_div64_0 clockRate {0}
set_instantiation_interface_parameter_value o_clk_rec_div64_0 clockRateKnown {false}
set_instantiation_interface_parameter_value o_clk_rec_div64_0 externallyDriven {false}
set_instantiation_interface_parameter_value o_clk_rec_div64_0 ptfSchematicName {}
set_instantiation_interface_sysinfo_parameter_value o_clk_rec_div64_0 clock_rate {0}
add_instantiation_interface_port o_clk_rec_div64_0 o_clk_rec_div64_0 clk 1 STD_LOGIC Output
add_instantiation_interface o_clk_rec_div66_0 clock OUTPUT
set_instantiation_interface_parameter_value o_clk_rec_div66_0 associatedDirectClock {}
set_instantiation_interface_parameter_value o_clk_rec_div66_0 clockRate {0}
set_instantiation_interface_parameter_value o_clk_rec_div66_0 clockRateKnown {false}
set_instantiation_interface_parameter_value o_clk_rec_div66_0 externallyDriven {false}
set_instantiation_interface_parameter_value o_clk_rec_div66_0 ptfSchematicName {}
set_instantiation_interface_sysinfo_parameter_value o_clk_rec_div66_0 clock_rate {0}
add_instantiation_interface_port o_clk_rec_div66_0 o_clk_rec_div66_0 clk 1 STD_LOGIC Output
add_instantiation_interface nonpcs_ports conduit INPUT
set_instantiation_interface_parameter_value nonpcs_ports associatedClock {}
set_instantiation_interface_parameter_value nonpcs_ports associatedReset {}
set_instantiation_interface_parameter_value nonpcs_ports prSafe {false}
add_instantiation_interface_port nonpcs_ports i_tx_skip_crc i_tx_skip_crc 1 STD_LOGIC Input
add_instantiation_interface_port nonpcs_ports o_rxstatus_data o_rxstatus_data 40 STD_LOGIC_VECTOR Output
add_instantiation_interface_port nonpcs_ports o_rxstatus_valid o_rxstatus_valid 1 STD_LOGIC Output
add_instantiation_interface pfc_ports conduit INPUT
set_instantiation_interface_parameter_value pfc_ports associatedClock {}
set_instantiation_interface_parameter_value pfc_ports associatedReset {}
set_instantiation_interface_parameter_value pfc_ports prSafe {false}
add_instantiation_interface_port pfc_ports i_tx_pfc i_tx_pfc 8 STD_LOGIC_VECTOR Input
add_instantiation_interface_port pfc_ports o_rx_pfc o_rx_pfc 8 STD_LOGIC_VECTOR Output
add_instantiation_interface pause_ports conduit INPUT
set_instantiation_interface_parameter_value pause_ports associatedClock {}
set_instantiation_interface_parameter_value pause_ports associatedReset {}
set_instantiation_interface_parameter_value pause_ports prSafe {false}
add_instantiation_interface_port pause_ports i_tx_pause i_tx_pause 1 STD_LOGIC Input
add_instantiation_interface_port pause_ports o_rx_pause o_rx_pause 1 STD_LOGIC Output
save_instantiation
add_component sys_iopll ip/sys/sys_iopll.ip altera_iopll sys_iopll 19.3.1
load_component sys_iopll
set_component_parameter_value gui_active_clk {0}
set_component_parameter_value gui_c_cnt_in_src0 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src1 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src2 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src3 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src4 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src5 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src6 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src7 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_c_cnt_in_src8 {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_cal_code_hex_file {iossm.hex}
set_component_parameter_value gui_cal_converge {0}
set_component_parameter_value gui_cal_error {cal_clean}
set_component_parameter_value gui_cascade_counter0 {0}
set_component_parameter_value gui_cascade_counter1 {0}
set_component_parameter_value gui_cascade_counter10 {0}
set_component_parameter_value gui_cascade_counter11 {0}
set_component_parameter_value gui_cascade_counter12 {0}
set_component_parameter_value gui_cascade_counter13 {0}
set_component_parameter_value gui_cascade_counter14 {0}
set_component_parameter_value gui_cascade_counter15 {0}
set_component_parameter_value gui_cascade_counter16 {0}
set_component_parameter_value gui_cascade_counter17 {0}
set_component_parameter_value gui_cascade_counter2 {0}
set_component_parameter_value gui_cascade_counter3 {0}
set_component_parameter_value gui_cascade_counter4 {0}
set_component_parameter_value gui_cascade_counter5 {0}
set_component_parameter_value gui_cascade_counter6 {0}
set_component_parameter_value gui_cascade_counter7 {0}
set_component_parameter_value gui_cascade_counter8 {0}
set_component_parameter_value gui_cascade_counter9 {0}
set_component_parameter_value gui_cascade_outclk_index {0}
set_component_parameter_value gui_clk_bad {0}
set_component_parameter_value gui_clock_name_global {0}
set_component_parameter_value gui_clock_name_string0 {outclk0}
set_component_parameter_value gui_clock_name_string1 {outclk1}
set_component_parameter_value gui_clock_name_string10 {outclk10}
set_component_parameter_value gui_clock_name_string11 {outclk11}
set_component_parameter_value gui_clock_name_string12 {outclk12}
set_component_parameter_value gui_clock_name_string13 {outclk13}
set_component_parameter_value gui_clock_name_string14 {outclk14}
set_component_parameter_value gui_clock_name_string15 {outclk15}
set_component_parameter_value gui_clock_name_string16 {outclk16}
set_component_parameter_value gui_clock_name_string17 {outclk17}
set_component_parameter_value gui_clock_name_string2 {outclk2}
set_component_parameter_value gui_clock_name_string3 {outclk3}
set_component_parameter_value gui_clock_name_string4 {outclk4}
set_component_parameter_value gui_clock_name_string5 {outclk5}
set_component_parameter_value gui_clock_name_string6 {outclk6}
set_component_parameter_value gui_clock_name_string7 {outclk7}
set_component_parameter_value gui_clock_name_string8 {outclk8}
set_component_parameter_value gui_clock_name_string9 {outclk9}
set_component_parameter_value gui_clock_to_compensate {0}
set_component_parameter_value gui_debug_mode {0}
set_component_parameter_value gui_divide_factor_c0 {6}
set_component_parameter_value gui_divide_factor_c1 {6}
set_component_parameter_value gui_divide_factor_c10 {6}
set_component_parameter_value gui_divide_factor_c11 {6}
set_component_parameter_value gui_divide_factor_c12 {6}
set_component_parameter_value gui_divide_factor_c13 {6}
set_component_parameter_value gui_divide_factor_c14 {6}
set_component_parameter_value gui_divide_factor_c15 {6}
set_component_parameter_value gui_divide_factor_c16 {6}
set_component_parameter_value gui_divide_factor_c17 {6}
set_component_parameter_value gui_divide_factor_c2 {6}
set_component_parameter_value gui_divide_factor_c3 {6}
set_component_parameter_value gui_divide_factor_c4 {6}
set_component_parameter_value gui_divide_factor_c5 {6}
set_component_parameter_value gui_divide_factor_c6 {6}
set_component_parameter_value gui_divide_factor_c7 {6}
set_component_parameter_value gui_divide_factor_c8 {6}
set_component_parameter_value gui_divide_factor_c9 {6}
set_component_parameter_value gui_divide_factor_n {1}
set_component_parameter_value gui_dps_cntr {C0}
set_component_parameter_value gui_dps_dir {Positive}
set_component_parameter_value gui_dps_num {1}
set_component_parameter_value gui_dsm_out_sel {1st_order}
set_component_parameter_value gui_duty_cycle0 {50.0}
set_component_parameter_value gui_duty_cycle1 {50.0}
set_component_parameter_value gui_duty_cycle10 {50.0}
set_component_parameter_value gui_duty_cycle11 {50.0}
set_component_parameter_value gui_duty_cycle12 {50.0}
set_component_parameter_value gui_duty_cycle13 {50.0}
set_component_parameter_value gui_duty_cycle14 {50.0}
set_component_parameter_value gui_duty_cycle15 {50.0}
set_component_parameter_value gui_duty_cycle16 {50.0}
set_component_parameter_value gui_duty_cycle17 {50.0}
set_component_parameter_value gui_duty_cycle2 {50.0}
set_component_parameter_value gui_duty_cycle3 {50.0}
set_component_parameter_value gui_duty_cycle4 {50.0}
set_component_parameter_value gui_duty_cycle5 {50.0}
set_component_parameter_value gui_duty_cycle6 {50.0}
set_component_parameter_value gui_duty_cycle7 {50.0}
set_component_parameter_value gui_duty_cycle8 {50.0}
set_component_parameter_value gui_duty_cycle9 {50.0}
set_component_parameter_value gui_en_adv_params {0}
set_component_parameter_value gui_en_dps_ports {0}
set_component_parameter_value gui_en_extclkout_ports {0}
set_component_parameter_value gui_en_iossm_reconf {0}
set_component_parameter_value gui_en_lvds_ports {Disabled}
set_component_parameter_value gui_en_periphery_ports {0}
set_component_parameter_value gui_en_phout_ports {0}
set_component_parameter_value gui_en_reconf {0}
set_component_parameter_value gui_enable_cascade_in {0}
set_component_parameter_value gui_enable_cascade_out {0}
set_component_parameter_value gui_enable_mif_dps {0}
set_component_parameter_value gui_enable_output_counter_cascading {0}
set_component_parameter_value gui_enable_permit_cal {0}
set_component_parameter_value gui_enable_upstream_out_clk {0}
set_component_parameter_value gui_existing_mif_file_path {~/pll.mif}
set_component_parameter_value gui_extclkout_0_source {C0}
set_component_parameter_value gui_extclkout_1_source {C0}
set_component_parameter_value gui_feedback_clock {Global Clock}
set_component_parameter_value gui_fix_vco_frequency {0}
set_component_parameter_value gui_fixed_vco_frequency {600.0}
set_component_parameter_value gui_fixed_vco_frequency_ps {1667.0}
set_component_parameter_value gui_frac_multiply_factor {1.0}
set_component_parameter_value gui_fractional_cout {32}
set_component_parameter_value gui_include_iossm {0}
set_component_parameter_value gui_location_type {I/O Bank}
set_component_parameter_value gui_lock_setting {Low Lock Time}
set_component_parameter_value gui_mif_config_name {unnamed}
set_component_parameter_value gui_mif_gen_options {Generate New MIF File}
set_component_parameter_value gui_multiply_factor {6}
set_component_parameter_value gui_new_mif_file_path {~/pll.mif}
set_component_parameter_value gui_number_of_clocks {1}
set_component_parameter_value gui_operation_mode {direct}
set_component_parameter_value gui_output_clock_frequency0 {300.0}
set_component_parameter_value gui_output_clock_frequency1 {100.0}
set_component_parameter_value gui_output_clock_frequency10 {100.0}
set_component_parameter_value gui_output_clock_frequency11 {100.0}
set_component_parameter_value gui_output_clock_frequency12 {100.0}
set_component_parameter_value gui_output_clock_frequency13 {100.0}
set_component_parameter_value gui_output_clock_frequency14 {100.0}
set_component_parameter_value gui_output_clock_frequency15 {100.0}
set_component_parameter_value gui_output_clock_frequency16 {100.0}
set_component_parameter_value gui_output_clock_frequency17 {100.0}
set_component_parameter_value gui_output_clock_frequency2 {100.0}
set_component_parameter_value gui_output_clock_frequency3 {100.0}
set_component_parameter_value gui_output_clock_frequency4 {100.0}
set_component_parameter_value gui_output_clock_frequency5 {100.0}
set_component_parameter_value gui_output_clock_frequency6 {100.0}
set_component_parameter_value gui_output_clock_frequency7 {100.0}
set_component_parameter_value gui_output_clock_frequency8 {100.0}
set_component_parameter_value gui_output_clock_frequency9 {100.0}
set_component_parameter_value gui_output_clock_frequency_ps0 {3333.333}
set_component_parameter_value gui_output_clock_frequency_ps1 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps10 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps11 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps12 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps13 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps14 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps15 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps16 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps17 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps2 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps3 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps4 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps5 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps6 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps7 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps8 {10000.0}
set_component_parameter_value gui_output_clock_frequency_ps9 {10000.0}
set_component_parameter_value gui_parameter_table_hex_file {seq_params_sim.hex}
set_component_parameter_value gui_phase_shift0 {0.0}
set_component_parameter_value gui_phase_shift1 {0.0}
set_component_parameter_value gui_phase_shift10 {0.0}
set_component_parameter_value gui_phase_shift11 {0.0}
set_component_parameter_value gui_phase_shift12 {0.0}
set_component_parameter_value gui_phase_shift13 {0.0}
set_component_parameter_value gui_phase_shift14 {0.0}
set_component_parameter_value gui_phase_shift15 {0.0}
set_component_parameter_value gui_phase_shift16 {0.0}
set_component_parameter_value gui_phase_shift17 {0.0}
set_component_parameter_value gui_phase_shift2 {0.0}
set_component_parameter_value gui_phase_shift3 {0.0}
set_component_parameter_value gui_phase_shift4 {0.0}
set_component_parameter_value gui_phase_shift5 {0.0}
set_component_parameter_value gui_phase_shift6 {0.0}
set_component_parameter_value gui_phase_shift7 {0.0}
set_component_parameter_value gui_phase_shift8 {0.0}
set_component_parameter_value gui_phase_shift9 {0.0}
set_component_parameter_value gui_phase_shift_deg0 {0.0}
set_component_parameter_value gui_phase_shift_deg1 {0.0}
set_component_parameter_value gui_phase_shift_deg10 {0.0}
set_component_parameter_value gui_phase_shift_deg11 {0.0}
set_component_parameter_value gui_phase_shift_deg12 {0.0}
set_component_parameter_value gui_phase_shift_deg13 {0.0}
set_component_parameter_value gui_phase_shift_deg14 {0.0}
set_component_parameter_value gui_phase_shift_deg15 {0.0}
set_component_parameter_value gui_phase_shift_deg16 {0.0}
set_component_parameter_value gui_phase_shift_deg17 {0.0}
set_component_parameter_value gui_phase_shift_deg2 {0.0}
set_component_parameter_value gui_phase_shift_deg3 {0.0}
set_component_parameter_value gui_phase_shift_deg4 {0.0}
set_component_parameter_value gui_phase_shift_deg5 {0.0}
set_component_parameter_value gui_phase_shift_deg6 {0.0}
set_component_parameter_value gui_phase_shift_deg7 {0.0}
set_component_parameter_value gui_phase_shift_deg8 {0.0}
set_component_parameter_value gui_phase_shift_deg9 {0.0}
set_component_parameter_value gui_phout_division {1}
set_component_parameter_value gui_pll_auto_reset {0}
set_component_parameter_value gui_pll_bandwidth_preset {Low}
set_component_parameter_value gui_pll_cal_done {0}
set_component_parameter_value gui_pll_cascading_mode {adjpllin}
set_component_parameter_value gui_pll_freqcal_en {1}
set_component_parameter_value gui_pll_freqcal_req_flag {1}
set_component_parameter_value gui_pll_m_cnt_in_src {c_m_cnt_in_src_ph_mux_clk}
set_component_parameter_value gui_pll_mode {Integer-N PLL}
set_component_parameter_value gui_pll_tclk_mux_en {0}
set_component_parameter_value gui_pll_tclk_sel {pll_tclk_m_src}
set_component_parameter_value gui_pll_type {S10_Simple}
set_component_parameter_value gui_pll_vco_freq_band_0 {pll_freq_clk0_band18}
set_component_parameter_value gui_pll_vco_freq_band_1 {pll_freq_clk1_band18}
set_component_parameter_value gui_prot_mode {UNUSED}
set_component_parameter_value gui_ps_units0 {ps}
set_component_parameter_value gui_ps_units1 {ps}
set_component_parameter_value gui_ps_units10 {ps}
set_component_parameter_value gui_ps_units11 {ps}
set_component_parameter_value gui_ps_units12 {ps}
set_component_parameter_value gui_ps_units13 {ps}
set_component_parameter_value gui_ps_units14 {ps}
set_component_parameter_value gui_ps_units15 {ps}
set_component_parameter_value gui_ps_units16 {ps}
set_component_parameter_value gui_ps_units17 {ps}
set_component_parameter_value gui_ps_units2 {ps}
set_component_parameter_value gui_ps_units3 {ps}
set_component_parameter_value gui_ps_units4 {ps}
set_component_parameter_value gui_ps_units5 {ps}
set_component_parameter_value gui_ps_units6 {ps}
set_component_parameter_value gui_ps_units7 {ps}
set_component_parameter_value gui_ps_units8 {ps}
set_component_parameter_value gui_ps_units9 {ps}
set_component_parameter_value gui_refclk1_frequency {100.0}
set_component_parameter_value gui_refclk_might_change {0}
set_component_parameter_value gui_refclk_switch {0}
set_component_parameter_value gui_reference_clock_frequency {100.0}
set_component_parameter_value gui_reference_clock_frequency_ps {10000.0}
set_component_parameter_value gui_simulation_type {0}
set_component_parameter_value gui_skip_sdc_generation {0}
set_component_parameter_value gui_switchover_delay {0}
set_component_parameter_value gui_switchover_mode {Automatic Switchover}
set_component_parameter_value gui_use_NDFB_modes {0}
set_component_parameter_value gui_use_coreclk {0}
set_component_parameter_value gui_use_locked {1}
set_component_parameter_value gui_use_logical {0}
set_component_parameter_value gui_usr_device_speed_grade {1}
set_component_parameter_value gui_vco_frequency {600.0}
set_component_parameter_value hp_qsys_scripting_mode {0}
set_component_parameter_value system_info_device_iobank_rev {}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_iopll
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.dts.compatible {altr,pll}
set_instantiation_assignment_value embeddedsw.dts.group {clock}
set_instantiation_assignment_value embeddedsw.dts.vendor {altr}
add_instantiation_interface reset reset INPUT
set_instantiation_interface_parameter_value reset associatedClock {}
set_instantiation_interface_parameter_value reset synchronousEdges {NONE}
set_instantiation_interface_assignment_value reset ui.blockdiagram.direction {input}
add_instantiation_interface_port reset rst reset 1 STD_LOGIC Input
add_instantiation_interface refclk clock INPUT
set_instantiation_interface_parameter_value refclk clockRate {100000000}
set_instantiation_interface_parameter_value refclk externallyDriven {false}
set_instantiation_interface_parameter_value refclk ptfSchematicName {}
set_instantiation_interface_assignment_value refclk ui.blockdiagram.direction {input}
add_instantiation_interface_port refclk refclk clk 1 STD_LOGIC Input
add_instantiation_interface locked conduit INPUT
set_instantiation_interface_parameter_value locked associatedClock {}
set_instantiation_interface_parameter_value locked associatedReset {}
set_instantiation_interface_parameter_value locked prSafe {false}
set_instantiation_interface_assignment_value locked ui.blockdiagram.direction {output}
add_instantiation_interface_port locked locked export 1 STD_LOGIC Output
add_instantiation_interface outclk0 clock OUTPUT
set_instantiation_interface_parameter_value outclk0 associatedDirectClock {}
set_instantiation_interface_parameter_value outclk0 clockRate {300000000}
set_instantiation_interface_parameter_value outclk0 clockRateKnown {true}
set_instantiation_interface_parameter_value outclk0 externallyDriven {false}
set_instantiation_interface_parameter_value outclk0 ptfSchematicName {}
set_instantiation_interface_assignment_value outclk0 ui.blockdiagram.direction {output}
set_instantiation_interface_sysinfo_parameter_value outclk0 clock_rate {300000000}
add_instantiation_interface_port outclk0 outclk_0 clk 1 STD_LOGIC Output
save_instantiation
add_component sys_jtag_uart ip/sys/sys_jtag_uart.ip altera_avalon_jtag_uart sys_jtag_uart 19.2.0
load_component sys_jtag_uart
set_component_parameter_value allowMultipleConnections {0}
set_component_parameter_value hubInstanceID {0}
set_component_parameter_value readBufferDepth {64}
set_component_parameter_value readIRQThreshold {8}
set_component_parameter_value simInputCharacterStream {}
set_component_parameter_value simInteractiveOptions {NO_INTERACTIVE_WINDOWS}
set_component_parameter_value useRegistersForReadBuffer {0}
set_component_parameter_value useRegistersForWriteBuffer {0}
set_component_parameter_value useRelativePathForSimFile {0}
set_component_parameter_value writeBufferDepth {64}
set_component_parameter_value writeIRQThreshold {8}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_jtag_uart
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.CMacro.READ_DEPTH {64}
set_instantiation_assignment_value embeddedsw.CMacro.READ_THRESHOLD {8}
set_instantiation_assignment_value embeddedsw.CMacro.WRITE_DEPTH {64}
set_instantiation_assignment_value embeddedsw.CMacro.WRITE_THRESHOLD {8}
set_instantiation_assignment_value embeddedsw.dts.compatible {altr,juart-1.0}
set_instantiation_assignment_value embeddedsw.dts.group {serial}
set_instantiation_assignment_value embeddedsw.dts.name {juart}
set_instantiation_assignment_value embeddedsw.dts.vendor {altr}
add_instantiation_interface clk clock INPUT
set_instantiation_interface_parameter_value clk clockRate {0}
set_instantiation_interface_parameter_value clk externallyDriven {false}
set_instantiation_interface_parameter_value clk ptfSchematicName {}
add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input
add_instantiation_interface reset reset INPUT
set_instantiation_interface_parameter_value reset associatedClock {clk}
set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT}
add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input
add_instantiation_interface avalon_jtag_slave avalon INPUT
set_instantiation_interface_parameter_value avalon_jtag_slave addressAlignment {NATIVE}
set_instantiation_interface_parameter_value avalon_jtag_slave addressGroup {0}
set_instantiation_interface_parameter_value avalon_jtag_slave addressSpan {2}
set_instantiation_interface_parameter_value avalon_jtag_slave addressUnits {WORDS}
set_instantiation_interface_parameter_value avalon_jtag_slave alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value avalon_jtag_slave associatedClock {clk}
set_instantiation_interface_parameter_value avalon_jtag_slave associatedReset {reset}
set_instantiation_interface_parameter_value avalon_jtag_slave bitsPerSymbol {8}
set_instantiation_interface_parameter_value avalon_jtag_slave bridgedAddressOffset {0}
set_instantiation_interface_parameter_value avalon_jtag_slave bridgesToMaster {}
set_instantiation_interface_parameter_value avalon_jtag_slave burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value avalon_jtag_slave burstcountUnits {WORDS}
set_instantiation_interface_parameter_value avalon_jtag_slave constantBurstBehavior {false}
set_instantiation_interface_parameter_value avalon_jtag_slave explicitAddressSpan {0}
set_instantiation_interface_parameter_value avalon_jtag_slave holdTime {0}
set_instantiation_interface_parameter_value avalon_jtag_slave interleaveBursts {false}
set_instantiation_interface_parameter_value avalon_jtag_slave isBigEndian {false}
set_instantiation_interface_parameter_value avalon_jtag_slave isFlash {false}
set_instantiation_interface_parameter_value avalon_jtag_slave isMemoryDevice {false}
set_instantiation_interface_parameter_value avalon_jtag_slave isNonVolatileStorage {false}
set_instantiation_interface_parameter_value avalon_jtag_slave linewrapBursts {false}
set_instantiation_interface_parameter_value avalon_jtag_slave maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value avalon_jtag_slave maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value avalon_jtag_slave minimumReadLatency {1}
set_instantiation_interface_parameter_value avalon_jtag_slave minimumResponseLatency {1}
set_instantiation_interface_parameter_value avalon_jtag_slave minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value avalon_jtag_slave prSafe {false}
set_instantiation_interface_parameter_value avalon_jtag_slave printableDevice {true}
set_instantiation_interface_parameter_value avalon_jtag_slave readLatency {0}
set_instantiation_interface_parameter_value avalon_jtag_slave readWaitStates {1}
set_instantiation_interface_parameter_value avalon_jtag_slave readWaitTime {1}
set_instantiation_interface_parameter_value avalon_jtag_slave registerIncomingSignals {false}
set_instantiation_interface_parameter_value avalon_jtag_slave registerOutgoingSignals {false}
set_instantiation_interface_parameter_value avalon_jtag_slave setupTime {0}
set_instantiation_interface_parameter_value avalon_jtag_slave timingUnits {Cycles}
set_instantiation_interface_parameter_value avalon_jtag_slave transparentBridge {false}
set_instantiation_interface_parameter_value avalon_jtag_slave waitrequestAllowance {0}
set_instantiation_interface_parameter_value avalon_jtag_slave wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value avalon_jtag_slave writeLatency {0}
set_instantiation_interface_parameter_value avalon_jtag_slave writeWaitStates {0}
set_instantiation_interface_parameter_value avalon_jtag_slave writeWaitTime {0}
set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isPrintableDevice {1}
set_instantiation_interface_sysinfo_parameter_value avalon_jtag_slave address_map {<address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value avalon_jtag_slave address_width {3}
set_instantiation_interface_sysinfo_parameter_value avalon_jtag_slave max_slave_data_width {32}
add_instantiation_interface_port avalon_jtag_slave av_chipselect chipselect 1 STD_LOGIC Input
add_instantiation_interface_port avalon_jtag_slave av_address address 1 STD_LOGIC Input
add_instantiation_interface_port avalon_jtag_slave av_read_n read_n 1 STD_LOGIC Input
add_instantiation_interface_port avalon_jtag_slave av_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port avalon_jtag_slave av_write_n write_n 1 STD_LOGIC Input
add_instantiation_interface_port avalon_jtag_slave av_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port avalon_jtag_slave av_waitrequest waitrequest 1 STD_LOGIC Output
add_instantiation_interface irq interrupt INPUT
set_instantiation_interface_parameter_value irq associatedAddressablePoint {avalon_jtag_slave}
set_instantiation_interface_parameter_value irq associatedClock {clk}
set_instantiation_interface_parameter_value irq associatedReset {reset}
set_instantiation_interface_parameter_value irq bridgedReceiverOffset {0}
set_instantiation_interface_parameter_value irq bridgesToReceiver {}
set_instantiation_interface_parameter_value irq irqScheme {NONE}
add_instantiation_interface_port irq av_irq irq 1 STD_LOGIC Output
save_instantiation
add_component sys_mm_to_st_tx ip/sys/sys_st_to_mm_rx_0.ip altera_avalon_fifo sys_st_to_mm_rx_0 19.1.0
load_component sys_mm_to_st_tx
set_component_parameter_value avalonMMAvalonMMDataWidth {32}
set_component_parameter_value avalonMMAvalonSTDataWidth {32}
set_component_parameter_value bitsPerSymbol {8}
set_component_parameter_value channelWidth {0}
set_component_parameter_value errorWidth {0}
set_component_parameter_value fifoDepth {512}
set_component_parameter_value fifoInputInterfaceOptions {AVALONMM_WRITE}
set_component_parameter_value fifoOutputInterfaceOptions {AVALONST_SOURCE}
set_component_parameter_value showHiddenFeatures {0}
set_component_parameter_value singleClockMode {1}
set_component_parameter_value singleResetMode {0}
set_component_parameter_value symbolsPerBeat {4}
set_component_parameter_value useBackpressure {1}
set_component_parameter_value useIRQ {1}
set_component_parameter_value usePacket {1}
set_component_parameter_value useReadControl {0}
set_component_parameter_value useRegister {0}
set_component_parameter_value useWriteControl {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_mm_to_st_tx
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.CMacro.AVALONMM_AVALONMM_DATA_WIDTH {32}
set_instantiation_assignment_value embeddedsw.CMacro.AVALONMM_AVALONST_DATA_WIDTH {32}
set_instantiation_assignment_value embeddedsw.CMacro.BITS_PER_SYMBOL {8}
set_instantiation_assignment_value embeddedsw.CMacro.CHANNEL_WIDTH {0}
set_instantiation_assignment_value embeddedsw.CMacro.ERROR_WIDTH {0}
set_instantiation_assignment_value embeddedsw.CMacro.FIFO_DEPTH {512}
set_instantiation_assignment_value embeddedsw.CMacro.SINGLE_CLOCK_MODE {1}
set_instantiation_assignment_value embeddedsw.CMacro.SYMBOLS_PER_BEAT {4}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONMM_READ_SLAVE {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONMM_WRITE_SLAVE {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONST_SINK {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONST_SOURCE {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_BACKPRESSURE {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_IRQ {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_PACKET {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_READ_CONTROL {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_REGISTER {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_WRITE_CONTROL {1}
add_instantiation_interface clk_in clock INPUT
set_instantiation_interface_parameter_value clk_in clockRate {0}
set_instantiation_interface_parameter_value clk_in externallyDriven {false}
set_instantiation_interface_parameter_value clk_in ptfSchematicName {}
add_instantiation_interface_port clk_in wrclock clk 1 STD_LOGIC Input
add_instantiation_interface reset_in reset INPUT
set_instantiation_interface_parameter_value reset_in associatedClock {clk_in}
set_instantiation_interface_parameter_value reset_in synchronousEdges {DEASSERT}
add_instantiation_interface_port reset_in reset_n reset_n 1 STD_LOGIC Input
add_instantiation_interface in avalon INPUT
set_instantiation_interface_parameter_value in addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value in addressGroup {0}
set_instantiation_interface_parameter_value in addressSpan {8}
set_instantiation_interface_parameter_value in addressUnits {WORDS}
set_instantiation_interface_parameter_value in alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value in associatedClock {clk_in}
set_instantiation_interface_parameter_value in associatedReset {reset_in}
set_instantiation_interface_parameter_value in bitsPerSymbol {8}
set_instantiation_interface_parameter_value in bridgedAddressOffset {0}
set_instantiation_interface_parameter_value in bridgesToMaster {}
set_instantiation_interface_parameter_value in burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value in burstcountUnits {WORDS}
set_instantiation_interface_parameter_value in constantBurstBehavior {false}
set_instantiation_interface_parameter_value in explicitAddressSpan {0}
set_instantiation_interface_parameter_value in holdTime {0}
set_instantiation_interface_parameter_value in interleaveBursts {false}
set_instantiation_interface_parameter_value in isBigEndian {false}
set_instantiation_interface_parameter_value in isFlash {false}
set_instantiation_interface_parameter_value in isMemoryDevice {false}
set_instantiation_interface_parameter_value in isNonVolatileStorage {false}
set_instantiation_interface_parameter_value in linewrapBursts {false}
set_instantiation_interface_parameter_value in maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value in maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value in minimumReadLatency {1}
set_instantiation_interface_parameter_value in minimumResponseLatency {1}
set_instantiation_interface_parameter_value in minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value in prSafe {false}
set_instantiation_interface_parameter_value in printableDevice {false}
set_instantiation_interface_parameter_value in readLatency {0}
set_instantiation_interface_parameter_value in readWaitStates {1}
set_instantiation_interface_parameter_value in readWaitTime {1}
set_instantiation_interface_parameter_value in registerIncomingSignals {false}
set_instantiation_interface_parameter_value in registerOutgoingSignals {false}
set_instantiation_interface_parameter_value in setupTime {0}
set_instantiation_interface_parameter_value in timingUnits {Cycles}
set_instantiation_interface_parameter_value in transparentBridge {false}
set_instantiation_interface_parameter_value in waitrequestAllowance {0}
set_instantiation_interface_parameter_value in wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value in writeLatency {0}
set_instantiation_interface_parameter_value in writeWaitStates {0}
set_instantiation_interface_parameter_value in writeWaitTime {0}
set_instantiation_interface_assignment_value in embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value in embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value in embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value in embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value in address_map {<address-map><slave name='in' start='0x0' end='0x8' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value in address_width {3}
set_instantiation_interface_sysinfo_parameter_value in max_slave_data_width {32}
add_instantiation_interface_port in avalonmm_write_slave_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in avalonmm_write_slave_write write 1 STD_LOGIC Input
add_instantiation_interface_port in avalonmm_write_slave_address address 1 STD_LOGIC Input
add_instantiation_interface_port in avalonmm_write_slave_waitrequest waitrequest 1 STD_LOGIC Output
add_instantiation_interface out avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out associatedClock {clk_in}
set_instantiation_interface_parameter_value out associatedReset {reset_in}
set_instantiation_interface_parameter_value out beatsPerCycle {1}
set_instantiation_interface_parameter_value out dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out emptyWithinPacket {false}
set_instantiation_interface_parameter_value out errorDescriptor {}
set_instantiation_interface_parameter_value out firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out maxChannel {0}
set_instantiation_interface_parameter_value out packetDescription {}
set_instantiation_interface_parameter_value out prSafe {false}
set_instantiation_interface_parameter_value out readyAllowance {0}
set_instantiation_interface_parameter_value out readyLatency {1}
set_instantiation_interface_parameter_value out symbolsPerBeat {4}
add_instantiation_interface_port out avalonst_source_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out avalonst_source_data data 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out avalonst_source_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out avalonst_source_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out avalonst_source_empty empty 2 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out avalonst_source_ready ready 1 STD_LOGIC Input
add_instantiation_interface in_csr avalon INPUT
set_instantiation_interface_parameter_value in_csr addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value in_csr addressGroup {0}
set_instantiation_interface_parameter_value in_csr addressSpan {32}
set_instantiation_interface_parameter_value in_csr addressUnits {WORDS}
set_instantiation_interface_parameter_value in_csr alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value in_csr associatedClock {clk_in}
set_instantiation_interface_parameter_value in_csr associatedReset {reset_in}
set_instantiation_interface_parameter_value in_csr bitsPerSymbol {8}
set_instantiation_interface_parameter_value in_csr bridgedAddressOffset {0}
set_instantiation_interface_parameter_value in_csr bridgesToMaster {}
set_instantiation_interface_parameter_value in_csr burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value in_csr burstcountUnits {WORDS}
set_instantiation_interface_parameter_value in_csr constantBurstBehavior {false}
set_instantiation_interface_parameter_value in_csr explicitAddressSpan {0}
set_instantiation_interface_parameter_value in_csr holdTime {0}
set_instantiation_interface_parameter_value in_csr interleaveBursts {false}
set_instantiation_interface_parameter_value in_csr isBigEndian {false}
set_instantiation_interface_parameter_value in_csr isFlash {false}
set_instantiation_interface_parameter_value in_csr isMemoryDevice {false}
set_instantiation_interface_parameter_value in_csr isNonVolatileStorage {false}
set_instantiation_interface_parameter_value in_csr linewrapBursts {false}
set_instantiation_interface_parameter_value in_csr maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value in_csr maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value in_csr minimumReadLatency {1}
set_instantiation_interface_parameter_value in_csr minimumResponseLatency {1}
set_instantiation_interface_parameter_value in_csr minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value in_csr prSafe {false}
set_instantiation_interface_parameter_value in_csr printableDevice {false}
set_instantiation_interface_parameter_value in_csr readLatency {0}
set_instantiation_interface_parameter_value in_csr readWaitStates {1}
set_instantiation_interface_parameter_value in_csr readWaitTime {1}
set_instantiation_interface_parameter_value in_csr registerIncomingSignals {false}
set_instantiation_interface_parameter_value in_csr registerOutgoingSignals {false}
set_instantiation_interface_parameter_value in_csr setupTime {0}
set_instantiation_interface_parameter_value in_csr timingUnits {Cycles}
set_instantiation_interface_parameter_value in_csr transparentBridge {false}
set_instantiation_interface_parameter_value in_csr waitrequestAllowance {0}
set_instantiation_interface_parameter_value in_csr wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value in_csr writeLatency {0}
set_instantiation_interface_parameter_value in_csr writeWaitStates {0}
set_instantiation_interface_parameter_value in_csr writeWaitTime {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value in_csr address_map {<address-map><slave name='in_csr' start='0x0' end='0x20' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value in_csr address_width {5}
set_instantiation_interface_sysinfo_parameter_value in_csr max_slave_data_width {32}
add_instantiation_interface_port in_csr wrclk_control_slave_address address 3 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in_csr wrclk_control_slave_read read 1 STD_LOGIC Input
add_instantiation_interface_port in_csr wrclk_control_slave_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in_csr wrclk_control_slave_write write 1 STD_LOGIC Input
add_instantiation_interface_port in_csr wrclk_control_slave_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface in_irq interrupt INPUT
set_instantiation_interface_parameter_value in_irq associatedAddressablePoint {in_csr}
set_instantiation_interface_parameter_value in_irq associatedClock {clk_in}
set_instantiation_interface_parameter_value in_irq associatedReset {reset_in}
set_instantiation_interface_parameter_value in_irq bridgedReceiverOffset {0}
set_instantiation_interface_parameter_value in_irq bridgesToReceiver {}
set_instantiation_interface_parameter_value in_irq irqScheme {NONE}
add_instantiation_interface_port in_irq wrclk_control_slave_irq irq 1 STD_LOGIC Output
save_instantiation
add_component sys_rst_bridge ip/sys/sys_rst_bridge.ip altera_reset_bridge sys_rst_bridge 19.2.0
load_component sys_rst_bridge
set_component_parameter_value ACTIVE_LOW_RESET {0}
set_component_parameter_value NUM_RESET_OUTPUTS {1}
set_component_parameter_value SYNCHRONOUS_EDGES {none}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_RESET_REQUEST {0}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_rst_bridge
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_reset reset INPUT
set_instantiation_interface_parameter_value in_reset associatedClock {}
set_instantiation_interface_parameter_value in_reset synchronousEdges {NONE}
add_instantiation_interface_port in_reset in_reset reset 1 STD_LOGIC Input
add_instantiation_interface out_reset reset OUTPUT
set_instantiation_interface_parameter_value out_reset associatedClock {}
set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset}
set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset}
set_instantiation_interface_parameter_value out_reset synchronousEdges {NONE}
add_instantiation_interface_port out_reset out_reset reset 1 STD_LOGIC Output
save_instantiation
add_component sys_st_to_mm_rx ip/sys/sys_fifo_0.ip altera_avalon_fifo fifo_0 19.1.0
load_component sys_st_to_mm_rx
set_component_parameter_value avalonMMAvalonMMDataWidth {32}
set_component_parameter_value avalonMMAvalonSTDataWidth {32}
set_component_parameter_value bitsPerSymbol {8}
set_component_parameter_value channelWidth {0}
set_component_parameter_value errorWidth {0}
set_component_parameter_value fifoDepth {512}
set_component_parameter_value fifoInputInterfaceOptions {AVALONST_SINK}
set_component_parameter_value fifoOutputInterfaceOptions {AVALONMM_READ}
set_component_parameter_value showHiddenFeatures {0}
set_component_parameter_value singleClockMode {1}
set_component_parameter_value singleResetMode {0}
set_component_parameter_value symbolsPerBeat {4}
set_component_parameter_value useBackpressure {1}
set_component_parameter_value useIRQ {1}
set_component_parameter_value usePacket {1}
set_component_parameter_value useReadControl {0}
set_component_parameter_value useRegister {0}
set_component_parameter_value useWriteControl {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_st_to_mm_rx
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.CMacro.AVALONMM_AVALONMM_DATA_WIDTH {32}
set_instantiation_assignment_value embeddedsw.CMacro.AVALONMM_AVALONST_DATA_WIDTH {32}
set_instantiation_assignment_value embeddedsw.CMacro.BITS_PER_SYMBOL {8}
set_instantiation_assignment_value embeddedsw.CMacro.CHANNEL_WIDTH {0}
set_instantiation_assignment_value embeddedsw.CMacro.ERROR_WIDTH {0}
set_instantiation_assignment_value embeddedsw.CMacro.FIFO_DEPTH {512}
set_instantiation_assignment_value embeddedsw.CMacro.SINGLE_CLOCK_MODE {1}
set_instantiation_assignment_value embeddedsw.CMacro.SYMBOLS_PER_BEAT {4}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONMM_READ_SLAVE {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONMM_WRITE_SLAVE {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONST_SINK {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_AVALONST_SOURCE {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_BACKPRESSURE {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_IRQ {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_PACKET {1}
set_instantiation_assignment_value embeddedsw.CMacro.USE_READ_CONTROL {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_REGISTER {0}
set_instantiation_assignment_value embeddedsw.CMacro.USE_WRITE_CONTROL {1}
add_instantiation_interface clk_in clock INPUT
set_instantiation_interface_parameter_value clk_in clockRate {0}
set_instantiation_interface_parameter_value clk_in externallyDriven {false}
set_instantiation_interface_parameter_value clk_in ptfSchematicName {}
add_instantiation_interface_port clk_in wrclock clk 1 STD_LOGIC Input
add_instantiation_interface reset_in reset INPUT
set_instantiation_interface_parameter_value reset_in associatedClock {clk_in}
set_instantiation_interface_parameter_value reset_in synchronousEdges {DEASSERT}
add_instantiation_interface_port reset_in reset_n reset_n 1 STD_LOGIC Input
add_instantiation_interface in avalon_streaming INPUT
set_instantiation_interface_parameter_value in associatedClock {clk_in}
set_instantiation_interface_parameter_value in associatedReset {reset_in}
set_instantiation_interface_parameter_value in beatsPerCycle {1}
set_instantiation_interface_parameter_value in dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in emptyWithinPacket {false}
set_instantiation_interface_parameter_value in errorDescriptor {}
set_instantiation_interface_parameter_value in firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in maxChannel {0}
set_instantiation_interface_parameter_value in packetDescription {}
set_instantiation_interface_parameter_value in prSafe {false}
set_instantiation_interface_parameter_value in readyAllowance {0}
set_instantiation_interface_parameter_value in readyLatency {1}
set_instantiation_interface_parameter_value in symbolsPerBeat {4}
add_instantiation_interface_port in avalonst_sink_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in avalonst_sink_data data 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in avalonst_sink_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in avalonst_sink_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in avalonst_sink_empty empty 2 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in avalonst_sink_ready ready 1 STD_LOGIC Output
add_instantiation_interface out avalon INPUT
set_instantiation_interface_parameter_value out addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value out addressGroup {0}
set_instantiation_interface_parameter_value out addressSpan {8}
set_instantiation_interface_parameter_value out addressUnits {WORDS}
set_instantiation_interface_parameter_value out alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value out associatedClock {clk_in}
set_instantiation_interface_parameter_value out associatedReset {reset_in}
set_instantiation_interface_parameter_value out bitsPerSymbol {8}
set_instantiation_interface_parameter_value out bridgedAddressOffset {0}
set_instantiation_interface_parameter_value out bridgesToMaster {}
set_instantiation_interface_parameter_value out burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value out burstcountUnits {WORDS}
set_instantiation_interface_parameter_value out constantBurstBehavior {false}
set_instantiation_interface_parameter_value out explicitAddressSpan {0}
set_instantiation_interface_parameter_value out holdTime {0}
set_instantiation_interface_parameter_value out interleaveBursts {false}
set_instantiation_interface_parameter_value out isBigEndian {false}
set_instantiation_interface_parameter_value out isFlash {false}
set_instantiation_interface_parameter_value out isMemoryDevice {false}
set_instantiation_interface_parameter_value out isNonVolatileStorage {false}
set_instantiation_interface_parameter_value out linewrapBursts {false}
set_instantiation_interface_parameter_value out maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value out maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value out minimumReadLatency {1}
set_instantiation_interface_parameter_value out minimumResponseLatency {1}
set_instantiation_interface_parameter_value out minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value out prSafe {false}
set_instantiation_interface_parameter_value out printableDevice {false}
set_instantiation_interface_parameter_value out readLatency {1}
set_instantiation_interface_parameter_value out readWaitStates {0}
set_instantiation_interface_parameter_value out readWaitTime {0}
set_instantiation_interface_parameter_value out registerIncomingSignals {false}
set_instantiation_interface_parameter_value out registerOutgoingSignals {false}
set_instantiation_interface_parameter_value out setupTime {0}
set_instantiation_interface_parameter_value out timingUnits {Cycles}
set_instantiation_interface_parameter_value out transparentBridge {false}
set_instantiation_interface_parameter_value out waitrequestAllowance {0}
set_instantiation_interface_parameter_value out wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value out writeLatency {0}
set_instantiation_interface_parameter_value out writeWaitStates {0}
set_instantiation_interface_parameter_value out writeWaitTime {0}
set_instantiation_interface_assignment_value out embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value out embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value out embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value out embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value out address_map {<address-map><slave name='out' start='0x0' end='0x8' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value out address_width {3}
set_instantiation_interface_sysinfo_parameter_value out max_slave_data_width {32}
add_instantiation_interface_port out avalonmm_read_slave_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out avalonmm_read_slave_read read 1 STD_LOGIC Input
add_instantiation_interface_port out avalonmm_read_slave_address address 1 STD_LOGIC Input
add_instantiation_interface_port out avalonmm_read_slave_waitrequest waitrequest 1 STD_LOGIC Output
add_instantiation_interface in_csr avalon INPUT
set_instantiation_interface_parameter_value in_csr addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value in_csr addressGroup {0}
set_instantiation_interface_parameter_value in_csr addressSpan {32}
set_instantiation_interface_parameter_value in_csr addressUnits {WORDS}
set_instantiation_interface_parameter_value in_csr alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value in_csr associatedClock {clk_in}
set_instantiation_interface_parameter_value in_csr associatedReset {reset_in}
set_instantiation_interface_parameter_value in_csr bitsPerSymbol {8}
set_instantiation_interface_parameter_value in_csr bridgedAddressOffset {0}
set_instantiation_interface_parameter_value in_csr bridgesToMaster {}
set_instantiation_interface_parameter_value in_csr burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value in_csr burstcountUnits {WORDS}
set_instantiation_interface_parameter_value in_csr constantBurstBehavior {false}
set_instantiation_interface_parameter_value in_csr explicitAddressSpan {0}
set_instantiation_interface_parameter_value in_csr holdTime {0}
set_instantiation_interface_parameter_value in_csr interleaveBursts {false}
set_instantiation_interface_parameter_value in_csr isBigEndian {false}
set_instantiation_interface_parameter_value in_csr isFlash {false}
set_instantiation_interface_parameter_value in_csr isMemoryDevice {false}
set_instantiation_interface_parameter_value in_csr isNonVolatileStorage {false}
set_instantiation_interface_parameter_value in_csr linewrapBursts {false}
set_instantiation_interface_parameter_value in_csr maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value in_csr maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value in_csr minimumReadLatency {1}
set_instantiation_interface_parameter_value in_csr minimumResponseLatency {1}
set_instantiation_interface_parameter_value in_csr minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value in_csr prSafe {false}
set_instantiation_interface_parameter_value in_csr printableDevice {false}
set_instantiation_interface_parameter_value in_csr readLatency {0}
set_instantiation_interface_parameter_value in_csr readWaitStates {1}
set_instantiation_interface_parameter_value in_csr readWaitTime {1}
set_instantiation_interface_parameter_value in_csr registerIncomingSignals {false}
set_instantiation_interface_parameter_value in_csr registerOutgoingSignals {false}
set_instantiation_interface_parameter_value in_csr setupTime {0}
set_instantiation_interface_parameter_value in_csr timingUnits {Cycles}
set_instantiation_interface_parameter_value in_csr transparentBridge {false}
set_instantiation_interface_parameter_value in_csr waitrequestAllowance {0}
set_instantiation_interface_parameter_value in_csr wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value in_csr writeLatency {0}
set_instantiation_interface_parameter_value in_csr writeWaitStates {0}
set_instantiation_interface_parameter_value in_csr writeWaitTime {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value in_csr embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value in_csr address_map {<address-map><slave name='in_csr' start='0x0' end='0x20' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value in_csr address_width {5}
set_instantiation_interface_sysinfo_parameter_value in_csr max_slave_data_width {32}
add_instantiation_interface_port in_csr wrclk_control_slave_address address 3 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in_csr wrclk_control_slave_read read 1 STD_LOGIC Input
add_instantiation_interface_port in_csr wrclk_control_slave_writedata writedata 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in_csr wrclk_control_slave_write write 1 STD_LOGIC Input
add_instantiation_interface_port in_csr wrclk_control_slave_readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface in_irq interrupt INPUT
set_instantiation_interface_parameter_value in_irq associatedAddressablePoint {in_csr}
set_instantiation_interface_parameter_value in_irq associatedClock {clk_in}
set_instantiation_interface_parameter_value in_irq associatedReset {reset_in}
set_instantiation_interface_parameter_value in_irq bridgedReceiverOffset {0}
set_instantiation_interface_parameter_value in_irq bridgesToReceiver {}
set_instantiation_interface_parameter_value in_irq irqScheme {NONE}
add_instantiation_interface_port in_irq wrclk_control_slave_irq irq 1 STD_LOGIC Output
save_instantiation
add_component sys_st_width_conv_32_to_512 ip/sys/sys_st_width_conv_32_to_512.ip altera_avalon_st_adapter sys_st_width_conv_32_to_64 19.2.0
load_component sys_st_width_conv_32_to_512
set_component_parameter_value SYNC_RESET {1}
set_component_parameter_value inBitsPerSymbol {8}
set_component_parameter_value inChannelWidth {0}
set_component_parameter_value inDataWidth {32}
set_component_parameter_value inErrorDescriptor {}
set_component_parameter_value inErrorWidth {0}
set_component_parameter_value inMaxChannel {0}
set_component_parameter_value inReadyLatency {0}
set_component_parameter_value inUseEmptyPort {1}
set_component_parameter_value inUsePackets {1}
set_component_parameter_value inUseReady {1}
set_component_parameter_value inUseValid {1}
set_component_parameter_value outChannelWidth {0}
set_component_parameter_value outDataWidth {512}
set_component_parameter_value outErrorDescriptor {}
set_component_parameter_value outErrorWidth {0}
set_component_parameter_value outMaxChannel {0}
set_component_parameter_value outReadyLatency {0}
set_component_parameter_value outUseEmptyPort {1}
set_component_parameter_value outUseReady {1}
set_component_parameter_value outUseValid {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_st_width_conv_32_to_512
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_clk_0 clock INPUT
set_instantiation_interface_parameter_value in_clk_0 clockRate {0}
set_instantiation_interface_parameter_value in_clk_0 externallyDriven {false}
set_instantiation_interface_parameter_value in_clk_0 ptfSchematicName {}
add_instantiation_interface_port in_clk_0 in_clk_0_clk clk 1 STD_LOGIC Input
add_instantiation_interface in_rst_0 reset INPUT
set_instantiation_interface_parameter_value in_rst_0 associatedClock {in_clk_0}
set_instantiation_interface_parameter_value in_rst_0 synchronousEdges {BOTH}
add_instantiation_interface_port in_rst_0 in_rst_0_reset reset 1 STD_LOGIC Input
add_instantiation_interface in_0 avalon_streaming INPUT
set_instantiation_interface_parameter_value in_0 associatedClock {in_clk_0}
set_instantiation_interface_parameter_value in_0 associatedReset {in_rst_0}
set_instantiation_interface_parameter_value in_0 beatsPerCycle {1}
set_instantiation_interface_parameter_value in_0 dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in_0 emptyWithinPacket {false}
set_instantiation_interface_parameter_value in_0 errorDescriptor {}
set_instantiation_interface_parameter_value in_0 firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in_0 highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in_0 maxChannel {0}
set_instantiation_interface_parameter_value in_0 packetDescription {}
set_instantiation_interface_parameter_value in_0 prSafe {false}
set_instantiation_interface_parameter_value in_0 readyAllowance {0}
set_instantiation_interface_parameter_value in_0 readyLatency {0}
set_instantiation_interface_parameter_value in_0 symbolsPerBeat {4}
add_instantiation_interface_port in_0 in_0_data data 32 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in_0 in_0_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in_0 in_0_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port in_0 in_0_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in_0 in_0_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in_0 in_0_empty empty 2 STD_LOGIC_VECTOR Input
add_instantiation_interface out_0 avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out_0 associatedClock {in_clk_0}
set_instantiation_interface_parameter_value out_0 associatedReset {in_rst_0}
set_instantiation_interface_parameter_value out_0 beatsPerCycle {1}
set_instantiation_interface_parameter_value out_0 dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out_0 emptyWithinPacket {false}
set_instantiation_interface_parameter_value out_0 errorDescriptor {}
set_instantiation_interface_parameter_value out_0 firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out_0 highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out_0 maxChannel {0}
set_instantiation_interface_parameter_value out_0 packetDescription {}
set_instantiation_interface_parameter_value out_0 prSafe {false}
set_instantiation_interface_parameter_value out_0 readyAllowance {0}
set_instantiation_interface_parameter_value out_0 readyLatency {0}
set_instantiation_interface_parameter_value out_0 symbolsPerBeat {64}
add_instantiation_interface_port out_0 out_0_data data 512 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out_0 out_0_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out_0 out_0_ready ready 1 STD_LOGIC Input
add_instantiation_interface_port out_0 out_0_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out_0 out_0_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out_0 out_0_empty empty 6 STD_LOGIC_VECTOR Output
save_instantiation
add_component sys_st_width_conv_512_to_32 ip/sys/sys_st_width_conv_512_to_32.ip altera_avalon_st_adapter sys_st_width_conv_64_to_32 19.2.0
load_component sys_st_width_conv_512_to_32
set_component_parameter_value SYNC_RESET {1}
set_component_parameter_value inBitsPerSymbol {8}
set_component_parameter_value inChannelWidth {0}
set_component_parameter_value inDataWidth {512}
set_component_parameter_value inErrorDescriptor {}
set_component_parameter_value inErrorWidth {0}
set_component_parameter_value inMaxChannel {0}
set_component_parameter_value inReadyLatency {0}
set_component_parameter_value inUseEmptyPort {1}
set_component_parameter_value inUsePackets {1}
set_component_parameter_value inUseReady {1}
set_component_parameter_value inUseValid {1}
set_component_parameter_value outChannelWidth {0}
set_component_parameter_value outDataWidth {32}
set_component_parameter_value outErrorDescriptor {}
set_component_parameter_value outErrorWidth {0}
set_component_parameter_value outMaxChannel {0}
set_component_parameter_value outReadyLatency {0}
set_component_parameter_value outUseEmptyPort {1}
set_component_parameter_value outUseReady {1}
set_component_parameter_value outUseValid {1}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_st_width_conv_512_to_32
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_clk_0 clock INPUT
set_instantiation_interface_parameter_value in_clk_0 clockRate {0}
set_instantiation_interface_parameter_value in_clk_0 externallyDriven {false}
set_instantiation_interface_parameter_value in_clk_0 ptfSchematicName {}
add_instantiation_interface_port in_clk_0 in_clk_0_clk clk 1 STD_LOGIC Input
add_instantiation_interface in_rst_0 reset INPUT
set_instantiation_interface_parameter_value in_rst_0 associatedClock {in_clk_0}
set_instantiation_interface_parameter_value in_rst_0 synchronousEdges {BOTH}
add_instantiation_interface_port in_rst_0 in_rst_0_reset reset 1 STD_LOGIC Input
add_instantiation_interface in_0 avalon_streaming INPUT
set_instantiation_interface_parameter_value in_0 associatedClock {in_clk_0}
set_instantiation_interface_parameter_value in_0 associatedReset {in_rst_0}
set_instantiation_interface_parameter_value in_0 beatsPerCycle {1}
set_instantiation_interface_parameter_value in_0 dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in_0 emptyWithinPacket {false}
set_instantiation_interface_parameter_value in_0 errorDescriptor {}
set_instantiation_interface_parameter_value in_0 firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in_0 highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in_0 maxChannel {0}
set_instantiation_interface_parameter_value in_0 packetDescription {}
set_instantiation_interface_parameter_value in_0 prSafe {false}
set_instantiation_interface_parameter_value in_0 readyAllowance {0}
set_instantiation_interface_parameter_value in_0 readyLatency {0}
set_instantiation_interface_parameter_value in_0 symbolsPerBeat {64}
add_instantiation_interface_port in_0 in_0_data data 512 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in_0 in_0_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in_0 in_0_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port in_0 in_0_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in_0 in_0_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in_0 in_0_empty empty 6 STD_LOGIC_VECTOR Input
add_instantiation_interface out_0 avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out_0 associatedClock {in_clk_0}
set_instantiation_interface_parameter_value out_0 associatedReset {in_rst_0}
set_instantiation_interface_parameter_value out_0 beatsPerCycle {1}
set_instantiation_interface_parameter_value out_0 dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out_0 emptyWithinPacket {false}
set_instantiation_interface_parameter_value out_0 errorDescriptor {}
set_instantiation_interface_parameter_value out_0 firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out_0 highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out_0 maxChannel {0}
set_instantiation_interface_parameter_value out_0 packetDescription {}
set_instantiation_interface_parameter_value out_0 prSafe {false}
set_instantiation_interface_parameter_value out_0 readyAllowance {0}
set_instantiation_interface_parameter_value out_0 readyLatency {0}
set_instantiation_interface_parameter_value out_0 symbolsPerBeat {4}
add_instantiation_interface_port out_0 out_0_data data 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out_0 out_0_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out_0 out_0_ready ready 1 STD_LOGIC Input
add_instantiation_interface_port out_0 out_0_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out_0 out_0_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out_0 out_0_empty empty 2 STD_LOGIC_VECTOR Output
save_instantiation
add_component sys_sysid ip/sys/sys_sysid.ip altera_avalon_sysid_qsys sys_sysid 19.1.2
load_component sys_sysid
set_component_parameter_value id {-87110914}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation sys_sysid
remove_instantiation_interfaces_and_ports
set_instantiation_assignment_value embeddedsw.CMacro.ID {-87110914}
set_instantiation_assignment_value embeddedsw.CMacro.TIMESTAMP {0}
set_instantiation_assignment_value embeddedsw.dts.compatible {altr,sysid-1.0}
set_instantiation_assignment_value embeddedsw.dts.group {sysid}
set_instantiation_assignment_value embeddedsw.dts.name {sysid}
set_instantiation_assignment_value embeddedsw.dts.params.id {-87110914}
set_instantiation_assignment_value embeddedsw.dts.params.timestamp {0}
set_instantiation_assignment_value embeddedsw.dts.vendor {altr}
add_instantiation_interface clk clock INPUT
set_instantiation_interface_parameter_value clk clockRate {0}
set_instantiation_interface_parameter_value clk externallyDriven {false}
set_instantiation_interface_parameter_value clk ptfSchematicName {}
add_instantiation_interface_port clk clock clk 1 STD_LOGIC Input
add_instantiation_interface reset reset INPUT
set_instantiation_interface_parameter_value reset associatedClock {clk}
set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT}
add_instantiation_interface_port reset reset_n reset_n 1 STD_LOGIC Input
add_instantiation_interface control_slave avalon INPUT
set_instantiation_interface_parameter_value control_slave addressAlignment {DYNAMIC}
set_instantiation_interface_parameter_value control_slave addressGroup {0}
set_instantiation_interface_parameter_value control_slave addressSpan {8}
set_instantiation_interface_parameter_value control_slave addressUnits {WORDS}
set_instantiation_interface_parameter_value control_slave alwaysBurstMaxBurst {false}
set_instantiation_interface_parameter_value control_slave associatedClock {clk}
set_instantiation_interface_parameter_value control_slave associatedReset {reset}
set_instantiation_interface_parameter_value control_slave bitsPerSymbol {8}
set_instantiation_interface_parameter_value control_slave bridgedAddressOffset {0}
set_instantiation_interface_parameter_value control_slave bridgesToMaster {}
set_instantiation_interface_parameter_value control_slave burstOnBurstBoundariesOnly {false}
set_instantiation_interface_parameter_value control_slave burstcountUnits {WORDS}
set_instantiation_interface_parameter_value control_slave constantBurstBehavior {false}
set_instantiation_interface_parameter_value control_slave explicitAddressSpan {0}
set_instantiation_interface_parameter_value control_slave holdTime {0}
set_instantiation_interface_parameter_value control_slave interleaveBursts {false}
set_instantiation_interface_parameter_value control_slave isBigEndian {false}
set_instantiation_interface_parameter_value control_slave isFlash {false}
set_instantiation_interface_parameter_value control_slave isMemoryDevice {false}
set_instantiation_interface_parameter_value control_slave isNonVolatileStorage {false}
set_instantiation_interface_parameter_value control_slave linewrapBursts {false}
set_instantiation_interface_parameter_value control_slave maximumPendingReadTransactions {0}
set_instantiation_interface_parameter_value control_slave maximumPendingWriteTransactions {0}
set_instantiation_interface_parameter_value control_slave minimumReadLatency {1}
set_instantiation_interface_parameter_value control_slave minimumResponseLatency {1}
set_instantiation_interface_parameter_value control_slave minimumUninterruptedRunLength {1}
set_instantiation_interface_parameter_value control_slave prSafe {false}
set_instantiation_interface_parameter_value control_slave printableDevice {false}
set_instantiation_interface_parameter_value control_slave readLatency {0}
set_instantiation_interface_parameter_value control_slave readWaitStates {1}
set_instantiation_interface_parameter_value control_slave readWaitTime {1}
set_instantiation_interface_parameter_value control_slave registerIncomingSignals {false}
set_instantiation_interface_parameter_value control_slave registerOutgoingSignals {false}
set_instantiation_interface_parameter_value control_slave setupTime {0}
set_instantiation_interface_parameter_value control_slave timingUnits {Cycles}
set_instantiation_interface_parameter_value control_slave transparentBridge {false}
set_instantiation_interface_parameter_value control_slave waitrequestAllowance {0}
set_instantiation_interface_parameter_value control_slave wellBehavedWaitrequest {false}
set_instantiation_interface_parameter_value control_slave writeLatency {0}
set_instantiation_interface_parameter_value control_slave writeWaitStates {0}
set_instantiation_interface_parameter_value control_slave writeWaitTime {0}
set_instantiation_interface_assignment_value control_slave embeddedsw.configuration.isFlash {0}
set_instantiation_interface_assignment_value control_slave embeddedsw.configuration.isMemoryDevice {0}
set_instantiation_interface_assignment_value control_slave embeddedsw.configuration.isNonVolatileStorage {0}
set_instantiation_interface_assignment_value control_slave embeddedsw.configuration.isPrintableDevice {0}
set_instantiation_interface_sysinfo_parameter_value control_slave address_map {<address-map><slave name='control_slave' start='0x0' end='0x8' datawidth='32' /></address-map>}
set_instantiation_interface_sysinfo_parameter_value control_slave address_width {3}
set_instantiation_interface_sysinfo_parameter_value control_slave max_slave_data_width {32}
add_instantiation_interface_port control_slave readdata readdata 32 STD_LOGIC_VECTOR Output
add_instantiation_interface_port control_slave address address 1 STD_LOGIC Input
save_instantiation
add_component tx_clk_converter ip/sys/sys_hs_clk_xer_0.ip hs_clk_xer hs_clk_xer_0 19.3.1
load_component tx_clk_converter
set_component_parameter_value BITS_PER_SYMBOL {8}
set_component_parameter_value CHANNEL_WIDTH {1}
set_component_parameter_value DATA_WIDTH {512}
set_component_parameter_value ERROR_WIDTH {1}
set_component_parameter_value MAX_CHANNEL {0}
set_component_parameter_value READY_SYNC_DEPTH {2}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_CHANNEL {0}
set_component_parameter_value USE_ERROR {0}
set_component_parameter_value USE_OUTPUT_PIPELINE {1}
set_component_parameter_value USE_PACKETS {1}
set_component_parameter_value VALID_SYNC_DEPTH {2}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation tx_clk_converter
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_clk clock INPUT
set_instantiation_interface_parameter_value in_clk clockRate {0}
set_instantiation_interface_parameter_value in_clk externallyDriven {false}
set_instantiation_interface_parameter_value in_clk ptfSchematicName {}
add_instantiation_interface_port in_clk in_clk clk 1 STD_LOGIC Input
add_instantiation_interface in_clk_reset reset INPUT
set_instantiation_interface_parameter_value in_clk_reset associatedClock {in_clk}
set_instantiation_interface_parameter_value in_clk_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port in_clk_reset in_reset reset 1 STD_LOGIC Input
add_instantiation_interface out_clk clock INPUT
set_instantiation_interface_parameter_value out_clk clockRate {0}
set_instantiation_interface_parameter_value out_clk externallyDriven {false}
set_instantiation_interface_parameter_value out_clk ptfSchematicName {}
add_instantiation_interface_port out_clk out_clk clk 1 STD_LOGIC Input
add_instantiation_interface out_clk_reset reset INPUT
set_instantiation_interface_parameter_value out_clk_reset associatedClock {out_clk}
set_instantiation_interface_parameter_value out_clk_reset synchronousEdges {DEASSERT}
add_instantiation_interface_port out_clk_reset out_reset reset 1 STD_LOGIC Input
add_instantiation_interface in avalon_streaming INPUT
set_instantiation_interface_parameter_value in associatedClock {in_clk}
set_instantiation_interface_parameter_value in associatedReset {in_clk_reset}
set_instantiation_interface_parameter_value in beatsPerCycle {1}
set_instantiation_interface_parameter_value in dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value in emptyWithinPacket {false}
set_instantiation_interface_parameter_value in errorDescriptor {}
set_instantiation_interface_parameter_value in firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value in highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value in maxChannel {0}
set_instantiation_interface_parameter_value in packetDescription {}
set_instantiation_interface_parameter_value in prSafe {false}
set_instantiation_interface_parameter_value in readyAllowance {0}
set_instantiation_interface_parameter_value in readyLatency {0}
set_instantiation_interface_parameter_value in symbolsPerBeat {1}
add_instantiation_interface_port in in_ready ready 1 STD_LOGIC Output
add_instantiation_interface_port in in_valid valid 1 STD_LOGIC Input
add_instantiation_interface_port in in_startofpacket startofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_endofpacket endofpacket 1 STD_LOGIC Input
add_instantiation_interface_port in in_empty empty 6 STD_LOGIC_VECTOR Input
add_instantiation_interface_port in in_data data 512 STD_LOGIC_VECTOR Input
add_instantiation_interface out avalon_streaming OUTPUT
set_instantiation_interface_parameter_value out associatedClock {out_clk}
set_instantiation_interface_parameter_value out associatedReset {out_clk_reset}
set_instantiation_interface_parameter_value out beatsPerCycle {1}
set_instantiation_interface_parameter_value out dataBitsPerSymbol {8}
set_instantiation_interface_parameter_value out emptyWithinPacket {false}
set_instantiation_interface_parameter_value out errorDescriptor {}
set_instantiation_interface_parameter_value out firstSymbolInHighOrderBits {true}
set_instantiation_interface_parameter_value out highOrderSymbolAtMSB {false}
set_instantiation_interface_parameter_value out maxChannel {0}
set_instantiation_interface_parameter_value out packetDescription {}
set_instantiation_interface_parameter_value out prSafe {false}
set_instantiation_interface_parameter_value out readyAllowance {0}
set_instantiation_interface_parameter_value out readyLatency {0}
set_instantiation_interface_parameter_value out symbolsPerBeat {1}
add_instantiation_interface_port out out_ready ready 1 STD_LOGIC Input
add_instantiation_interface_port out out_valid valid 1 STD_LOGIC Output
add_instantiation_interface_port out out_startofpacket startofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_endofpacket endofpacket 1 STD_LOGIC Output
add_instantiation_interface_port out out_empty empty 6 STD_LOGIC_VECTOR Output
add_instantiation_interface_port out out_data data 512 STD_LOGIC_VECTOR Output
save_instantiation
add_component tx_rst_bridge ip/sys/sys_rst_bridge.ip altera_reset_bridge sys_rst_bridge 19.2.0
load_component tx_rst_bridge
set_component_parameter_value ACTIVE_LOW_RESET {0}
set_component_parameter_value NUM_RESET_OUTPUTS {1}
set_component_parameter_value SYNCHRONOUS_EDGES {none}
set_component_parameter_value SYNC_RESET {0}
set_component_parameter_value USE_RESET_REQUEST {0}
set_component_project_property HIDE_FROM_IP_CATALOG {false}
save_component
load_instantiation tx_rst_bridge
remove_instantiation_interfaces_and_ports
add_instantiation_interface in_reset reset INPUT
set_instantiation_interface_parameter_value in_reset associatedClock {}
set_instantiation_interface_parameter_value in_reset synchronousEdges {NONE}
add_instantiation_interface_port in_reset in_reset reset 1 STD_LOGIC Input
add_instantiation_interface out_reset reset OUTPUT
set_instantiation_interface_parameter_value out_reset associatedClock {}
set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset}
set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset}
set_instantiation_interface_parameter_value out_reset synchronousEdges {NONE}
add_instantiation_interface_port out_reset out_reset reset 1 STD_LOGIC Output
save_instantiation
# add wirelevel expressions
# preserve ports for debug
# add the connections
add_connection rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.syncResets {FALSE}
set_connection_parameter_value rx_clk_converter.out/sys_st_width_conv_512_to_32.in_0 qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection rx_rst_bridge.out_reset/rx_clk_converter.in_clk_reset
set_connection_parameter_value rx_rst_bridge.out_reset/rx_clk_converter.in_clk_reset clockDomainSysInfo {1}
set_connection_parameter_value rx_rst_bridge.out_reset/rx_clk_converter.in_clk_reset clockResetSysInfo {}
set_connection_parameter_value rx_rst_bridge.out_reset/rx_clk_converter.in_clk_reset resetDomainSysInfo {1}
add_connection rx_rst_bridge.out_reset/st_dc_fifo_rx.clk_reset
set_connection_parameter_value rx_rst_bridge.out_reset/st_dc_fifo_rx.clk_reset clockDomainSysInfo {1}
set_connection_parameter_value rx_rst_bridge.out_reset/st_dc_fifo_rx.clk_reset clockResetSysInfo {}
set_connection_parameter_value rx_rst_bridge.out_reset/st_dc_fifo_rx.clk_reset resetDomainSysInfo {1}
add_connection st_dc_fifo_rx.out/rx_clk_converter.in
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.syncResets {FALSE}
set_connection_parameter_value st_dc_fifo_rx.out/rx_clk_converter.in qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection st_sc_fifo_tx.out/sys_e_tile.tx_streaming
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.syncResets {FALSE}
set_connection_parameter_value st_sc_fifo_tx.out/sys_e_tile.tx_streaming qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection sys_clk_bridge.out_clk/sys_e_tile.i_reconfig_clk
set_connection_parameter_value sys_clk_bridge.out_clk/sys_e_tile.i_reconfig_clk clockDomainSysInfo {7}
set_connection_parameter_value sys_clk_bridge.out_clk/sys_e_tile.i_reconfig_clk clockRateSysInfo {100000000.0}
set_connection_parameter_value sys_clk_bridge.out_clk/sys_e_tile.i_reconfig_clk clockResetSysInfo {}
set_connection_parameter_value sys_clk_bridge.out_clk/sys_e_tile.i_reconfig_clk resetDomainSysInfo {7}
add_connection sys_clk_bridge.out_clk/sys_iopll.refclk
set_connection_parameter_value sys_clk_bridge.out_clk/sys_iopll.refclk clockDomainSysInfo {7}
set_connection_parameter_value sys_clk_bridge.out_clk/sys_iopll.refclk clockRateSysInfo {100000000.0}
set_connection_parameter_value sys_clk_bridge.out_clk/sys_iopll.refclk clockResetSysInfo {}
set_connection_parameter_value sys_clk_bridge.out_clk/sys_iopll.refclk resetDomainSysInfo {7}
add_connection sys_cpu.data_manager/st_dc_fifo_rx.csr
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr baseAddress {0x002100a0}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/st_dc_fifo_rx.csr slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/st_sc_fifo_tx.csr
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr baseAddress {0x00210080}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/st_sc_fifo_tx.csr slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_cpu.dm_agent
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent baseAddress {0x00200000}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.dm_agent slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_cpu.timer_sw_agent
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent baseAddress {0x00210000}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu.timer_sw_agent slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_cpu_ram.s1
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 baseAddress {0x0000}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_cpu_ram.s1 slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave baseAddress {0x002100c8}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_jtag_uart.avalon_jtag_slave slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_mm_to_st_tx.in
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in baseAddress {0x002100b8}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_mm_to_st_tx.in_csr
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr baseAddress {0x00210060}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_mm_to_st_tx.in_csr slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_st_to_mm_rx.in_csr
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr baseAddress {0x00210040}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.in_csr slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_st_to_mm_rx.out
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out baseAddress {0x002100b0}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_st_to_mm_rx.out slaveDataWidthSysInfo {-1}
add_connection sys_cpu.data_manager/sys_sysid.control_slave
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /><slave name='sys_cpu.timer_sw_agent' start='0x210000' end='0x210040' datawidth='32' /><slave name='sys_st_to_mm_rx.in_csr' start='0x210040' end='0x210060' datawidth='32' /><slave name='sys_mm_to_st_tx.in_csr' start='0x210060' end='0x210080' datawidth='32' /><slave name='st_sc_fifo_tx.csr' start='0x210080' end='0x2100A0' datawidth='32' /><slave name='st_dc_fifo_rx.csr' start='0x2100A0' end='0x2100B0' datawidth='32' /><slave name='sys_st_to_mm_rx.out' start='0x2100B0' end='0x2100B8' datawidth='32' /><slave name='sys_mm_to_st_tx.in' start='0x2100B8' end='0x2100C0' datawidth='32' /><slave name='sys_sysid.control_slave' start='0x2100C0' end='0x2100C8' datawidth='32' /><slave name='sys_jtag_uart.avalon_jtag_slave' start='0x2100C8' end='0x2100D0' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave arbitrationPriority {1}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave baseAddress {0x002100c0}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave defaultConnection {0}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave domainAlias {}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.data_manager/sys_sysid.control_slave slaveDataWidthSysInfo {-1}
add_connection sys_cpu.instruction_manager/sys_cpu.dm_agent
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent arbitrationPriority {1}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent baseAddress {0x00200000}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent defaultConnection {0}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent domainAlias {}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu.dm_agent slaveDataWidthSysInfo {-1}
add_connection sys_cpu.instruction_manager/sys_cpu_ram.s1
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 addressMapSysInfo {<address-map><slave name='sys_cpu_ram.s1' start='0x0' end='0x1E8480' datawidth='32' /><slave name='sys_cpu.dm_agent' start='0x200000' end='0x210000' datawidth='32' /></address-map>}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 addressWidthSysInfo {22}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 arbitrationPriority {1}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 baseAddress {0x0000}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 defaultConnection {0}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 domainAlias {}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.enableAllPipelines {TRUE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.syncResets {TRUE}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_cpu.instruction_manager/sys_cpu_ram.s1 slaveDataWidthSysInfo {-1}
add_connection sys_cpu.platform_irq_rx/sys_jtag_uart.irq
set_connection_parameter_value sys_cpu.platform_irq_rx/sys_jtag_uart.irq interruptsUsedSysInfo {7}
set_connection_parameter_value sys_cpu.platform_irq_rx/sys_jtag_uart.irq irqNumber {0}
add_connection sys_cpu.platform_irq_rx/sys_mm_to_st_tx.in_irq
set_connection_parameter_value sys_cpu.platform_irq_rx/sys_mm_to_st_tx.in_irq interruptsUsedSysInfo {7}
set_connection_parameter_value sys_cpu.platform_irq_rx/sys_mm_to_st_tx.in_irq irqNumber {2}
add_connection sys_cpu.platform_irq_rx/sys_st_to_mm_rx.in_irq
set_connection_parameter_value sys_cpu.platform_irq_rx/sys_st_to_mm_rx.in_irq interruptsUsedSysInfo {7}
set_connection_parameter_value sys_cpu.platform_irq_rx/sys_st_to_mm_rx.in_irq irqNumber {1}
add_connection sys_e_tile.o_clk_pll_div64_0/rx_clk_converter.in_clk
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/rx_clk_converter.in_clk clockDomainSysInfo {10}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/rx_clk_converter.in_clk clockRateSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/rx_clk_converter.in_clk clockResetSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/rx_clk_converter.in_clk resetDomainSysInfo {10}
add_connection sys_e_tile.o_clk_pll_div64_0/st_dc_fifo_rx.clk
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_dc_fifo_rx.clk clockDomainSysInfo {10}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_dc_fifo_rx.clk clockRateSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_dc_fifo_rx.clk clockResetSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_dc_fifo_rx.clk resetDomainSysInfo {10}
add_connection sys_e_tile.o_clk_pll_div64_0/st_sc_fifo_tx.clk
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_sc_fifo_tx.clk clockDomainSysInfo {10}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_sc_fifo_tx.clk clockRateSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_sc_fifo_tx.clk clockResetSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/st_sc_fifo_tx.clk resetDomainSysInfo {10}
add_connection sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_rx
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_rx clockDomainSysInfo {10}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_rx clockRateSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_rx clockResetSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_rx resetDomainSysInfo {10}
add_connection sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_tx
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_tx clockDomainSysInfo {10}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_tx clockRateSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_tx clockResetSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/sys_e_tile.i_clk_tx resetDomainSysInfo {10}
add_connection sys_e_tile.o_clk_pll_div64_0/tx_clk_converter.out_clk
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/tx_clk_converter.out_clk clockDomainSysInfo {10}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/tx_clk_converter.out_clk clockRateSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/tx_clk_converter.out_clk clockResetSysInfo {}
set_connection_parameter_value sys_e_tile.o_clk_pll_div64_0/tx_clk_converter.out_clk resetDomainSysInfo {10}
add_connection sys_e_tile.rx_streaming/st_dc_fifo_rx.in
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.syncResets {FALSE}
set_connection_parameter_value sys_e_tile.rx_streaming/st_dc_fifo_rx.in qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection sys_iopll.outclk0/rx_clk_converter.out_clk
set_connection_parameter_value sys_iopll.outclk0/rx_clk_converter.out_clk clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/rx_clk_converter.out_clk clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/rx_clk_converter.out_clk clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/rx_clk_converter.out_clk resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_cpu.clk
set_connection_parameter_value sys_iopll.outclk0/sys_cpu.clk clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_cpu.clk clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_cpu.clk clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_cpu.clk resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_cpu_ram.clk1
set_connection_parameter_value sys_iopll.outclk0/sys_cpu_ram.clk1 clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_cpu_ram.clk1 clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_cpu_ram.clk1 clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_cpu_ram.clk1 resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_jtag_uart.clk
set_connection_parameter_value sys_iopll.outclk0/sys_jtag_uart.clk clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_jtag_uart.clk clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_jtag_uart.clk clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_jtag_uart.clk resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_mm_to_st_tx.clk_in
set_connection_parameter_value sys_iopll.outclk0/sys_mm_to_st_tx.clk_in clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_mm_to_st_tx.clk_in clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_mm_to_st_tx.clk_in clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_mm_to_st_tx.clk_in resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_st_to_mm_rx.clk_in
set_connection_parameter_value sys_iopll.outclk0/sys_st_to_mm_rx.clk_in clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_st_to_mm_rx.clk_in clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_st_to_mm_rx.clk_in clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_st_to_mm_rx.clk_in resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_st_width_conv_32_to_512.in_clk_0
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_32_to_512.in_clk_0 clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_32_to_512.in_clk_0 clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_32_to_512.in_clk_0 clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_32_to_512.in_clk_0 resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_st_width_conv_512_to_32.in_clk_0
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_512_to_32.in_clk_0 clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_512_to_32.in_clk_0 clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_512_to_32.in_clk_0 clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_st_width_conv_512_to_32.in_clk_0 resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/sys_sysid.clk
set_connection_parameter_value sys_iopll.outclk0/sys_sysid.clk clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/sys_sysid.clk clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/sys_sysid.clk clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/sys_sysid.clk resetDomainSysInfo {11}
add_connection sys_iopll.outclk0/tx_clk_converter.in_clk
set_connection_parameter_value sys_iopll.outclk0/tx_clk_converter.in_clk clockDomainSysInfo {11}
set_connection_parameter_value sys_iopll.outclk0/tx_clk_converter.in_clk clockRateSysInfo {300000000.0}
set_connection_parameter_value sys_iopll.outclk0/tx_clk_converter.in_clk clockResetSysInfo {}
set_connection_parameter_value sys_iopll.outclk0/tx_clk_converter.in_clk resetDomainSysInfo {11}
add_connection sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.syncResets {FALSE}
set_connection_parameter_value sys_mm_to_st_tx.out/sys_st_width_conv_32_to_512.in_0 qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection sys_rst_bridge.out_reset/rx_clk_converter.out_clk_reset
set_connection_parameter_value sys_rst_bridge.out_reset/rx_clk_converter.out_clk_reset clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/rx_clk_converter.out_clk_reset clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/rx_clk_converter.out_clk_reset resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_cpu.reset
set_connection_parameter_value sys_rst_bridge.out_reset/sys_cpu.reset clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_cpu.reset clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_cpu.reset resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_cpu_ram.reset1
set_connection_parameter_value sys_rst_bridge.out_reset/sys_cpu_ram.reset1 clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_cpu_ram.reset1 clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_cpu_ram.reset1 resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_iopll.reset
set_connection_parameter_value sys_rst_bridge.out_reset/sys_iopll.reset clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_iopll.reset clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_iopll.reset resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_jtag_uart.reset
set_connection_parameter_value sys_rst_bridge.out_reset/sys_jtag_uart.reset clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_jtag_uart.reset clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_jtag_uart.reset resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_mm_to_st_tx.reset_in
set_connection_parameter_value sys_rst_bridge.out_reset/sys_mm_to_st_tx.reset_in clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_mm_to_st_tx.reset_in clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_mm_to_st_tx.reset_in resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_st_to_mm_rx.reset_in
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_to_mm_rx.reset_in clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_to_mm_rx.reset_in clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_to_mm_rx.reset_in resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_st_width_conv_32_to_512.in_rst_0
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_width_conv_32_to_512.in_rst_0 clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_width_conv_32_to_512.in_rst_0 clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_width_conv_32_to_512.in_rst_0 resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_st_width_conv_512_to_32.in_rst_0
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_width_conv_512_to_32.in_rst_0 clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_width_conv_512_to_32.in_rst_0 clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_st_width_conv_512_to_32.in_rst_0 resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/sys_sysid.reset
set_connection_parameter_value sys_rst_bridge.out_reset/sys_sysid.reset clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_sysid.reset clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/sys_sysid.reset resetDomainSysInfo {8}
add_connection sys_rst_bridge.out_reset/tx_clk_converter.in_clk_reset
set_connection_parameter_value sys_rst_bridge.out_reset/tx_clk_converter.in_clk_reset clockDomainSysInfo {8}
set_connection_parameter_value sys_rst_bridge.out_reset/tx_clk_converter.in_clk_reset clockResetSysInfo {}
set_connection_parameter_value sys_rst_bridge.out_reset/tx_clk_converter.in_clk_reset resetDomainSysInfo {8}
add_connection sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.syncResets {FALSE}
set_connection_parameter_value sys_st_width_conv_32_to_512.out_0/tx_clk_converter.in qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.syncResets {FALSE}
set_connection_parameter_value sys_st_width_conv_512_to_32.out_0/sys_st_to_mm_rx.in qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection tx_clk_converter.out/st_sc_fifo_tx.in
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.clockCrossingAdapter {HANDSHAKE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.enableAllPipelines {FALSE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.enableEccProtection {FALSE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.enableInstrumentation {FALSE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.insertDefaultSlave {FALSE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.interconnectResetSource {DEFAULT}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.interconnectType {STANDARD}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.maxAdditionalLatency {1}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.optimizeRdFifoSize {FALSE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.piplineType {PIPELINE_STAGE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.responseFifoType {REGISTER_BASED}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.syncResets {FALSE}
set_connection_parameter_value tx_clk_converter.out/st_sc_fifo_tx.in qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER}
add_connection tx_rst_bridge.out_reset/st_sc_fifo_tx.clk_reset
set_connection_parameter_value tx_rst_bridge.out_reset/st_sc_fifo_tx.clk_reset clockDomainSysInfo {9}
set_connection_parameter_value tx_rst_bridge.out_reset/st_sc_fifo_tx.clk_reset clockResetSysInfo {}
set_connection_parameter_value tx_rst_bridge.out_reset/st_sc_fifo_tx.clk_reset resetDomainSysInfo {9}
add_connection tx_rst_bridge.out_reset/tx_clk_converter.out_clk_reset
set_connection_parameter_value tx_rst_bridge.out_reset/tx_clk_converter.out_clk_reset clockDomainSysInfo {9}
set_connection_parameter_value tx_rst_bridge.out_reset/tx_clk_converter.out_clk_reset clockResetSysInfo {}
set_connection_parameter_value tx_rst_bridge.out_reset/tx_clk_converter.out_clk_reset resetDomainSysInfo {9}
# add the exports
set_interface_property rx_rst EXPORT_OF rx_rst_bridge.in_reset
set_interface_property in_clk EXPORT_OF sys_clk_bridge.in_clk
set_interface_property i_csr_rst_n EXPORT_OF sys_e_tile.i_csr_rst_n
set_interface_property i_tx_rst_n EXPORT_OF sys_e_tile.i_tx_rst_n
set_interface_property i_rx_rst_n EXPORT_OF sys_e_tile.i_rx_rst_n
set_interface_property serial_p EXPORT_OF sys_e_tile.serial_p
set_interface_property serial_n EXPORT_OF sys_e_tile.serial_n
set_interface_property i_reconfig_reset EXPORT_OF sys_e_tile.i_reconfig_reset
set_interface_property i_clk_ref EXPORT_OF sys_e_tile.i_clk_ref_0
set_interface_property in_rst EXPORT_OF sys_rst_bridge.in_reset
set_interface_property tx_rst EXPORT_OF tx_rst_bridge.in_reset
# set values for exposed HDL parameters
set_domain_assignment sys_cpu.data_manager qsys_mm.burstAdapterImplementation GENERIC_CONVERTER
set_domain_assignment sys_cpu.data_manager qsys_mm.clockCrossingAdapter HANDSHAKE
set_domain_assignment sys_cpu.data_manager qsys_mm.enableAllPipelines TRUE
set_domain_assignment sys_cpu.data_manager qsys_mm.enableEccProtection FALSE
set_domain_assignment sys_cpu.data_manager qsys_mm.enableInstrumentation FALSE
set_domain_assignment sys_cpu.data_manager qsys_mm.insertDefaultSlave FALSE
set_domain_assignment sys_cpu.data_manager qsys_mm.interconnectResetSource DEFAULT
set_domain_assignment sys_cpu.data_manager qsys_mm.interconnectType STANDARD
set_domain_assignment sys_cpu.data_manager qsys_mm.maxAdditionalLatency 1
set_domain_assignment sys_cpu.data_manager qsys_mm.optimizeRdFifoSize FALSE
set_domain_assignment sys_cpu.data_manager qsys_mm.piplineType PIPELINE_STAGE
set_domain_assignment sys_cpu.data_manager qsys_mm.responseFifoType REGISTER_BASED
set_domain_assignment sys_cpu.data_manager qsys_mm.syncResets TRUE
set_domain_assignment sys_cpu.data_manager qsys_mm.widthAdapterImplementation GENERIC_CONVERTER
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="rx_clk_converter">
<datum __value="_sortIndex" value="14" type="int" />
</element>
<element __value="rx_rst_bridge">
<datum __value="_sortIndex" value="16" type="int" />
</element>
<element __value="st_dc_fifo_rx">
<datum __value="_sortIndex" value="15" type="int" />
</element>
<element __value="st_dc_fifo_rx.csr">
<datum __value="baseAddress" value="2162848" type="String" />
</element>
<element __value="st_sc_fifo_tx">
<datum __value="_sortIndex" value="12" type="int" />
</element>
<element __value="st_sc_fifo_tx.csr">
<datum __value="baseAddress" value="2162816" type="String" />
</element>
<element __value="sys_clk_bridge">
<datum __value="_sortIndex" value="0" type="int" />
</element>
<element __value="sys_cpu">
<datum __value="_sortIndex" value="3" type="int" />
</element>
<element __value="sys_cpu.dm_agent">
<datum __value="baseAddress" value="2097152" type="String" />
</element>
<element __value="sys_cpu.timer_sw_agent">
<datum __value="baseAddress" value="2162688" type="String" />
</element>
<element __value="sys_cpu_ram">
<datum __value="_sortIndex" value="4" type="int" />
</element>
<element __value="sys_cpu_ram.s1">
<datum __value="baseAddress" value="0" type="String" />
</element>
<element __value="sys_e_tile">
<datum __value="_sortIndex" value="17" type="int" />
</element>
<element __value="sys_iopll">
<datum __value="_sortIndex" value="2" type="int" />
</element>
<element __value="sys_jtag_uart">
<datum __value="_sortIndex" value="5" type="int" />
</element>
<element __value="sys_jtag_uart.avalon_jtag_slave">
<datum __value="baseAddress" value="2162888" type="String" />
</element>
<element __value="sys_mm_to_st_tx">
<datum __value="_sortIndex" value="8" type="int" />
</element>
<element __value="sys_mm_to_st_tx.in">
<datum __value="baseAddress" value="2162872" type="String" />
</element>
<element __value="sys_mm_to_st_tx.in_csr">
<datum __value="baseAddress" value="2162784" type="String" />
</element>
<element __value="sys_rst_bridge">
<datum __value="_sortIndex" value="1" type="int" />
</element>
<element __value="sys_st_to_mm_rx">
<datum __value="_sortIndex" value="7" type="int" />
</element>
<element __value="sys_st_to_mm_rx.in_csr">
<datum __value="baseAddress" value="2162752" type="String" />
</element>
<element __value="sys_st_to_mm_rx.out">
<datum __value="baseAddress" value="2162864" type="String" />
</element>
<element __value="sys_st_width_conv_32_to_512">
<datum __value="_sortIndex" value="9" type="int" />
</element>
<element __value="sys_st_width_conv_512_to_32">
<datum __value="_sortIndex" value="10" type="int" />
</element>
<element __value="sys_sysid">
<datum __value="_sortIndex" value="6" type="int" />
</element>
<element __value="sys_sysid.control_slave">
<datum __value="baseAddress" value="2162880" type="String" />
</element>
<element __value="tx_clk_converter">
<datum __value="_sortIndex" value="11" type="int" />
</element>
<element __value="tx_rst_bridge">
<datum __value="_sortIndex" value="13" type="int" />
</element>
</bonusData>
}
set_module_property FILE {sys.qsys}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {sys}
# save the system
sync_sysinfo_parameters
save_system sys
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_sys
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters
E-Tile Ethernet IP への入力について
細かい話ですが1点、E-Tile Ethernet IP への入力でハマった部分があるので記載しておきます。
E-Tile Ethernet IP のドキュメント をよく読むと、下記のような記載がありました。
You must send each TX data packet without intermediate IDLE cycles.
E-Tile Ethernet IP へのStream 入力は隙間なく行う必要があるとのことです。
当初これに気づかずに動かしていたため、Stream が1 beat のARP は通るにも関わらず、2 beat 以上になるPing は通らないという事象が発生していました。
この問題に対処するため、前段のFIFO Memory TX で Store and forward mode を有効化しています。
lwIP を利用したコードの実装
Nios V 上で動作させるコードを実装していきます。
lwIP はARP, Ping, TCP/IP 通信の処理を行ってくれるライブラリですが、ハードウェアとやり取りする部分や、TCP パケットを受け取ったあとの処理は別途実装する必要があります。
実装が必要なのは大きく分けて下記4つです。
- Nios V <-> FIFO Memory の通信を行うコード
- Ethernet Packet を送受信するコード
- TCP の動作を規定するコード(=Application)
- 各種設定とmain 関数
なお今回は、lwIP のエッセンスを説明しやすくするため、非常にシンプルな実装としています。
より詳細な実装方法については下記ページが詳しいです。ありがたく参考にさせていただきました。
BitVisorのlwIP機能の解説 - Qiita
Nios V <-> FIFO Memory の通信を行うコード
最も物理層に近いコードです。FIFO Memory とのデータのやりとりを記載しています。
使用している関数については 24.6. Intel FPGA Avalon FIFO Memory API に記載があります。
fifo_memory_read_write
main.c
int read_data() {
const alt_u32 address = SYS_ST_TO_MM_RX_OUT_BASE;
const alt_u32 ctrl_address = SYS_ST_TO_MM_RX_IN_CSR_BASE;
int empty = 1;
while (empty != 0) {
empty = altera_avalon_fifo_read_status(ctrl_address,
ALTERA_AVALON_FIFO_STATUS_E_MSK);
}
return altera_avalon_fifo_read_fifo(address, ctrl_address);
}
int read_info() {
const alt_u32 address = SYS_ST_TO_MM_RX_OUT_BASE;
return altera_avalon_fifo_read_other_info(address);
}
void write_data(const u8_t* data) {
const alt_u32 address = SYS_MM_TO_ST_TX_IN_BASE;
const alt_u32 ctrl_address = SYS_MM_TO_ST_TX_IN_CSR_BASE;
// Pack data to word
u32_t word = 0;
for (int idx = 0; idx < sizeof(u32_t); idx++) {
word |= *(data + idx) << (idx * 8);
}
int ret = ALTERA_AVALON_FIFO_FULL;
do {
ret = altera_avalon_fifo_write_fifo(address,
ctrl_address,
word);
} while (ret == ALTERA_AVALON_FIFO_FULL);
}
void write_info(const alt_u32 data) {
const alt_u32 address = SYS_MM_TO_ST_TX_IN_BASE;
const alt_u32 ctrl_address = SYS_MM_TO_ST_TX_IN_CSR_BASE;
int ret = ALTERA_AVALON_FIFO_FULL;
do {
ret = altera_avalon_fifo_write_other_info(address,
ctrl_address,
data);
} while (ret == ALTERA_AVALON_FIFO_FULL);
}
void set_start_of_packet() {
write_info(0x1);
}
void set_end_of_packet(const uint32_t empty) {
write_info((0x02 << empty) | 0x2);
}
Ethernet Packet を送受信するコード
Ethernet Packet 送受信にそれぞれ使用される関数です。
受信側はFIFO Memory からデータを読み出し、EtherType がIP/ARP の場合に以降の処理をlwIP に任せます。
main.c
void rx_recv(struct netif *netif) {
// Create pbuf in order to store read data
struct pbuf* p = pbuf_alloc(PBUF_RAW, MAX_PKT_SIZE, PBUF_POOL);
u8_t* payload = (u8_t*)p->payload;
// Read data while EoP
int len = 0;
bool start_of_packet = false;
bool end_of_packet = false;
while (!end_of_packet) {
// Read data & info from FIFO Memory
const u32_t RxWord = read_data();
const int info = read_info();
// Check SoP & EoP
start_of_packet = ((info & 0x1) == 0x1);
end_of_packet = ((info & 0x2) == 0x2);
// If SoP, reset len
if (start_of_packet) len = 0;
// Upack data from RxWord
for (int idx = 0; idx < sizeof(u32_t); idx++) {
payload[len + idx] = (RxWord >> (idx * 8)) & 0xff;
}
// Update len
len += sizeof(u32_t);
// If EoP, fix len
if (end_of_packet) {
const uint32_t empty = (info >> 2) & 0x1F;
len -= empty;
}
}
// Check Ethernet header & Pass data to lwIP
const struct eth_hdr *ethhdr = p->payload;
err_t ret;
switch (htons(ethhdr->type)) {
case ETHTYPE_IP:
case ETHTYPE_ARP:
ret = netif->input(p, netif); // To be continued in lwIP.
if (ret != ERR_OK) {
pbuf_free(p);
}
break;
default:
pbuf_free(p);
}
}
送信側はlwIP から受け取った送信データをFIFO Memory に書き込みます。
main.c
err_t tx_send(struct netif *netif, struct pbuf *p) {
// Copy data to pkt_buf
int length = p->len;
u8_t pkt_buf[MAX_PKT_SIZE];
memcpy(pkt_buf, p->payload, length);
// Padding to minimum ethernet packet size
if (length < 60) {
length = 60;
}
// Send packet
for (int len = 0; len < length; len += sizeof(u32_t)) {
// Write info to FIFO Memory if SoP or EoP
if (len == 0) {
set_start_of_packet();
} else if ((len + sizeof(u32_t)) >= length) {
const uint32_t empty = (len + sizeof(u32_t)) - length;
set_end_of_packet(empty);
}
// Write data to FIFO Memory
write_data(&pkt_buf[len]);
}
return ERR_OK;
}
TCP の動作を規定するコード(=Application)
まず、TCP のコネクションを確立するために、socket(), bind(), listen() に相当する処理が必要ですが、これらはmain 関数で行うため後述します。
TCP のコネクションが確立されたとき、lwIP は accept_callback() を呼び出します。(そうするように後述のmain 関数で設定します。)
accept_callback() 内部では、TCP のデータを受信したときにrecv_callback() を呼び出すよう設定します。
このようにすることで、確立されたコネクションからのデータはすべてrecv_callback() で処理されるようになります。
main.c
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err) {
// Set callback function when recv TCP data
tcp_recv(newpcb, recv_callback);
return ERR_OK;
}
recv_callback() 内部は以下のようになっていて、TCP のデータを受信したことを通知した後に、その受信したデータを破棄します。
何も処理を行わない意味のないコードのように見えますが、後述のiperf を利用してTCP/IP の性能を測定するにはこれで十分です。
main.c
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
struct pbuf *p, err_t err) {
// Tell TCP data received
tcp_recved(tpcb, p->len);
// Trash data
if (p != NULL) pbuf_free(p);
return ERR_OK;
}
各種設定とmain 関数
最後に各種設定を行う関数とmain 関数を記載しておきます。
先述のsocket(), bind(), listen() に相当する処理、および accept_callback() の設定はこの中で行っています。
setting_main
main.c
#define MTU 1500
#define MAX_PKT_SIZE (MTU + 18)
err_t init_netif(struct netif* netif) {
netif->name[0] = 'I';
netif->name[1] = 'F';
netif->output = etharp_output;
netif->linkoutput = tx_send;
netif->mtu = MTU;
netif->flags = NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
netif->hwaddr_len = ETHARP_HWADDR_LEN;
for (int i = 0; i < netif->hwaddr_len; i++) {
netif->hwaddr[i] = ((unsigned char*)netif->state)[i];
}
return ERR_OK;
}
int main() {
// Initialize lwIP
lwip_init();
// Specify MAC Address
unsigned char macaddr[] = {0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc};
// Specify IP Address, Net Mask, Default Gateway
ip_addr_t ipaddr, netmask, gateway;
IP4_ADDR(&ipaddr, 192, 168, 1, 8);
IP4_ADDR(&netmask, 255, 255, 255, 0);
IP4_ADDR(&gateway, 192, 168, 1, 1);
// Specify TCP port
u16_t tcp_port = 5001;
// Setup netif
struct netif netif;
netif_add(&netif, &ipaddr, &netmask, &gateway,
macaddr, init_netif, ethernet_input);
netif_set_up(&netif);
// Setup TCP
struct tcp_pcb *tcp_pcb;
// Creates a new TCP protocol control block
tcp_pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
// Binds the connection to a local port number and IP address.
tcp_bind(tcp_pcb, IP_ANY_TYPE, tcp_port);
// Set the state of the connection to be LISTEN
tcp_pcb = tcp_listen_with_backlog(tcp_pcb, 1);
// Set callback function when accept TCP packet
tcp_accept(tcp_pcb, accept_callback);
// Receive data infinitely
while (1) {
rx_recv(&netif);
}
return 0;
}
一点重要なのが、FIFO Memory からデータを読み出すrx_recv() が無限ループで動作しているということです。
このコードはデータ受信を契機にして動作するようになっていて、TCP のコネクション確立後は下図のような関係になっています。
また、他にも必要なファイルがあるので記載しておきます。
lwipopts.h
lwipopts.h
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
#define NO_SYS 1
#define SYS_LIGHTWEIGHT_PROT 0
#define LWIP_TIMERS 0
#define LWIP_NETCONN 0
#define LWIP_SOCKET 0
#define LWIP_ARP 1
#define LWIP_IPV4 1
#define LWIP_IPV6 0
#define LWIP_UDPLITE 0
#define LWIP_TCP 1
#define LWIP_STATS 0
#define LWIP_DEBUG 0
#define MEM_ALIGNMENT 8
#define MEMP_NUM_TCP_PCB 16
#endif /* __LWIPOPTS_H__ */
cc.h
cc.h
// Empty file
lwIP を利用したコードのビルド
lwIP を利用したコードのビルドについて記載します。
まずはlwIP 本体を下記コマンドでclone します。
$ git clone https://git.savannah.gnu.org/git/lwip.git/ -b STABLE-2_1_3_RELEASE
続いて、Nios V 向けのコードのビルドを行います。
Nios V のコードのビルド方法は
Nios® V processor インストール、Hello World実行編 - Qiita に詳しく記載されています。(参考にさせていただきました。ありがとうございます。)
下記4ステップです。
- BSP 生成
- CMakeLists.txt 生成
- Makefile 生成
- app.elf 生成
lwIP を利用するために「2. CMakeLists.txt 生成」後、下記を追記します。
/path/to/lwip/ には先程clone したディレクトリを記載してください
set(LWIP_DIR /path/to/lwip/)
set(LWIP_INCLUDE_DIRS ${LWIP_DIR}/src/include/ ${CMAKE_CURRENT_SOURCE_DIR}/include/)
include(${LWIP_DIR}/src/Filelists.cmake)
target_include_directories(app.elf
PRIVATE
${LWIP_INCLUDE_DIRS}
)
target_link_libraries(app.elf
PRIVATE
lwipcore
)
その後3, 4 を実施すると、lwIP を含んだelf ファイルが生成されます。
動作確認
FPGA デザインとlwIP のコードが完成したら、それぞれを書き込んだ後に動作確認を行います。
動作確認にはFPGA に対してEthernet パケットを送るものが必要なので、NIC とケーブルを用意し以下のような構成としました。
Host PC 上で下記各種コマンドを入力し、通信ができることを確認します。
arping
$ arping -c3 -I ens2f1 192.168.1.8
ARPING 192.168.1.8 from 192.168.1.5 ens2f1
Unicast reply from 192.168.1.8 [12:34:56:78:9A:BC] 1.006ms
Unicast reply from 192.168.1.8 [12:34:56:78:9A:BC] 1.007ms
Unicast reply from 192.168.1.8 [12:34:56:78:9A:BC] 1.007ms
Sent 3 probes (1 broadcast(s))
Received 3 response(s)
ping
$ ping -c3 192.168.1.8
PING 192.168.1.8 (192.168.1.8) 56(84) bytes of data.
64 bytes from 192.168.1.8: icmp_seq=1 ttl=255 time=0.701 ms
64 bytes from 192.168.1.8: icmp_seq=2 ttl=255 time=0.709 ms
64 bytes from 192.168.1.8: icmp_seq=3 ttl=255 time=0.715 ms
--- 192.168.1.8 ping statistics ---
3 packets transmitted, 3 received, 0% packet loss, time 2033ms
rtt min/avg/max/mdev = 0.701/0.708/0.715/0.022 ms
iperf (TCP/IP)
$ iperf -c 192.168.1.8
------------------------------------------------------------
Client connecting to 192.168.1.8, TCP port 5001
TCP window size: 45.0 KByte (default)
------------------------------------------------------------
[ 3] local 192.168.1.5 port 34190 connected with 192.168.1.8 port 5001
[ ID] Interval Transfer Bandwidth
[ 3] 0.0-10.0 sec 2.25 MBytes 1.88 Mbits/sec
まとめ
E-Tile, Nios V, lwIP を利用し、TCP/IP 通信することができました。
ただ、実はNIC, ケーブルともに 100 Gbps 対応のものを使用しているにもかかわらず、iperf の結果を見ると1.88 Mbps しか出ていません。
FPGA 側でSGDMAC を使用したり、Nios V の処理性能を向上させるといった手段も考えられますが、根本的にはTCP/IP の処理をソフトウェアではなくハードウェアにオフロードする必要があるでしょう。
詳細情報
開発環境
- FPGA Board: Intel Agilex F-Series FPGA Development Kit (ES)
- Device: AGFB014R24A2E3VR0
- FPGA Tool: Intel Quartus Prime Version 22.2.0
- SW Build: riscv-none-embed-gcc (xPack GNU RISC-V Embedded GCC x86_64) 10.2.0
- Library: lwIP @ STABLE-2_1_3_RELEASE
テスト環境
- Host PC:
- CPU: Intel(R) Xeon(R) CPU E5-2620 v3 @ 2.40GHz
- MEM: DDR4-2133 32GB
- OS: Ubuntu 18.04.3 LTS
- NIC: NVIDIA Mellanox ConnectX-5 MT27800 Family
- Cable: FS Mellanox MCP1600-C003 Compatible 100G QSFP28 Passive Direct Attach Copper Twinax Cable
- SW: iperf version 2.0.10