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石谷 太一

@taichi-ishitani

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229Contributions
15
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23
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Rubyが得意な半導体屋です (Ruby/SystemVerilog/UVMが得意)

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神奈川

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FPGACPUHDLRISC-VVHDLSystemVerilogElixirRSpecUVMVerilogRubyGitHub

$ analyze @taichi-ishitani

posted articles:
  • SystemVerilog:80%
  • Verilog:67%
  • FPGA:67%
  • VHDL:40%
  • HDL:33%
answered questions:
  • No data
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taichi-ishitani

@taichi-ishitani(石谷 太一)

2019-08-29

制御レジスタ (CSR) を自動生成する

  • Verilog
  • FPGA
  • SystemVerilog
  • VHDL
  • UVM
23
taichi-ishitani

@taichi-ishitani(石谷 太一)

2020-12-05

出木杉君演算子 inside

  • Verilog
  • FPGA
  • HDL
  • SystemVerilog
12
taichi-ishitani

@taichi-ishitani(石谷 太一)

2021-11-30

[SystemVerilog] interface と function を組み合わせると便利ですよ、という話

  • Verilog
  • FPGA
  • HDL
  • SystemVerilog
17
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