石谷太一

@taichi-ishitani

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Rubyが得意な半導体屋です (Ruby/SystemVerilog/UVMが得意)

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神奈川

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FPGA CPU HDL RISC-V VHDL SystemVerilog Elixir RSpec UVM Verilog Ruby GitHub

$ analyze @taichi-ishitani

posted articles:

SystemVerilog:81%
FPGA:69%
Verilog:63%
VHDL:38%
HDL:31%

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