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石谷太一

@taichi-ishitani

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Rubyが得意な半導体屋です (Ruby/SystemVerilog/UVMが得意)

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神奈川

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FPGA CPU HDL RISC-V VHDL SystemVerilog Elixir RSpec UVM Verilog Ruby GitHub

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セキュリティキャンプ2026 L2 プロセッサゼミ参加記

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セキュリティキャンプ2026 L2 プロセッサゼミ参加記

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検証環境とテストシナリオの実装方針

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[Veryl] Genericsの使いどころ

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RTL で依存性の注入（っぽいこと）をする

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[Veryl] Genericsの使いどころ

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[Veryl] Genericsの使いどころ

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いろいろなラウンドロビンを実装する！

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型のパラメータ化と interface based typedef

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[Veryl] Genericsの使いどころ