主にLSIハード設計／検証の人。あとC/C++も。最近は趣味でラズパイやPythonや機械学習やディープラーニングも。
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$ analyze @vega77
posted articles:
- SystemVerilog:74%
- Verilog:48%
- VerilogHDL:39%
- HDL:30%
- UVM:30%
answered questions:
- No data