VHDL のソースコードを必要な分だけを正しく読み込むためのスクリプト

はじめに

この記事では VHDL を使って RTL を書いて論理合成をしたりシミュレーションしたりする際に、必要なソースコードだけを、正しい順序で読み込むために便利な ruby スクリプトを紹介します。

リポジトリ

ruby のスクリプトは以下の URL で公開しています(なぜか二つのファイルに分れてしまってますがご容赦ください)。

• https://github.com/ikwzm/PipeWork/blob/master/tools/vhdl-archiver.rb
• https://github.com/ikwzm/PipeWork/blob/master/tools/lib/pipework/vhdl-reader.rb

解決したい問題

この記事で紹介する ruby スクリプトは、VHDL のソースコードを軽く解析して、階層構造や依存関係を把握して、必要最小限かつ正しく処理系が読み込める順番でファイル名を出力します。

ソースコードを読み込む順序に気を付ける必要がある

VHDL を使って RTL を書いて論理合成をしたりシミュレーションしたりする際、処理系によっては、読み込むファイルの順番に気をつけなければならないことがあります。

例えば次のような階層化されたモジュールを読み込む場合、

sub.vhd

library ieee;
use     ieee.std_logic_1164.all;
entity  sub is
    generic (
        W : integer
    );
    port(
        I : in  std_logic_vector(W-1 downto 0);
        O : out std_logic_vector(W-1 downto 0)
    );
end sub;

main.vhd

library ieee;
use     ieee.std_logic_1164.all;
entity  main is
end     main;
architecture model of main is
    signal i : std_logic_vector(9 downto 0);
    signal o : std_logic_vector(9 downto 0);
begin
    u: entity work.sub generic map(W => 10) port map (I => i,O => o);
end model;

例えば、GHDLの場合、いきなり main.vhd を読み込むと次のようなエラーが出ます。

shell$ ghdl -a -C --work=work main.vhd
main.vhd:9:20:error: unit "sub" not found in library "work"
    u: entity work.sub generic map(W => 10) port map (I => i,O => o);

このような場合は、まず sub.vhd を読み込んでから main.vhd を読み込まなくてはなりません。

shell$ ghdl -a -C --work=work sub.vhd
shell$ ghdl -a -C --work=work main.vhd

大量の VHDL のソースコードがあるような規模のプロジェクトの場合、これらを正しい順序で読み込むのはかなり面倒なことになります。

不要なファイルも読み込んでしまう

VHDL で記述する際、ライブラリを使うことがあります。そして、ライブラリには多くの package や entity が含まれていることがあります。そのうち必要最小限の package や entity だけを読み込みたい場合もあります。

また、一つの entity に対して architecutre が複数ある場合、指定された architecutre のみを読み込みたい場合もあります。

使用例

この記事では『VHDL で書くマージソーター(ArgSort IP)』@Qiita で紹介した ArgSort IP を使って、使用例を示します。

ダウンロード

shell$ git clone --recursive -b 1.6.2 https://github.com/ikwzm/Merge_Sorter.git

Vivado でシミュレーション

Requirement

• Xilinx Vivado 2025.1

shell$ cd Merge_Sorter/sim/vivado/argsort_axi

Create add_files.tcl

このディレクトリに次のような add_files.yml というファイルがあります。

Merge_Sorter/sim/vivado/argsort_axi/add_files.yml

- Library:
    Name     :  pipework
    Print    :  true
    Format   :  "add_vhdl_file sources_1 #{library_name} #{file_name}"
    Use      :  ["SDPRAM(MODEL)", "QUEUE_ARBITER(ONE_HOT_ARCH)"]
    PathList :  ["../../../PipeWork/src/"]

- Library:
    Name     :  merge_sorter
    Print    :  true
    Format   :  "add_vhdl_file sources_1 #{library_name} #{file_name}"
    PathList :  ["../../../src/main/vhdl"]

- Library:
    Name     :  dummy_plug
    Print    :  true
    Format   :  "add_vhdl_file sim_1     #{library_name} #{file_name}"
    Exclude  :  ["../../../Dummy_Plug/src/main/vhdl/core/sync_alt.vhd"]
    PathList :  ["../../../Dummy_Plug/src/main/vhdl/"]

- Library:
    Name     :  work
    Print    :  true
    Format   :  "add_vhdl_file sim_1     #{library_name} #{file_name}"
    PathList :  ["../../../src/test/vhdl"]
    Top      :  ["ArgSort_AXI_Test_Bench"]

add_files.yml にはライブラリごとに、Name(ライブラリの名前)、PathList(ファイルがあるパスのリスト)、Format(出力するさいのフォーマット)が記述されています。また、Top には階層構造のトップになる entity 名のリストが記載されています。

この add_files.yml を次のように ruby スクリプトに食わせると add_files.tcl というファイルが出来ます。

shell$ ../../../PipeWork/tools/vhdl-archiver.rb --config add_files.yml > add_files.tcl

add_files.tcl（ちょっと長いので折り畳み)

Merge_Sorter/sim/vivado/argsort_axi/add_files.tcl

add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/components.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_intake_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_outlet_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pipeline_register_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_types.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/count_down_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/count_up_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/delay_adjuster.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/delay_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_intake_manifold_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_outlet_manifold_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/justifier.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pipeline_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/reducer.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/syncronizer.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/syncronizer_input_pending_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_components.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_control_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_components.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_data_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/chopper.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pool_intake_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pool_outlet_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_controller_intake_side.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_controller_outlet_side.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_flow_syncronizer.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_data_outlet_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_address_channel_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_transfer_queue.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_arbiter.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_receiver.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/sdpram.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_stream_intake_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_stream_outlet_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_read_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_write_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_tree_arbiter.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_read_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_write_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_decoder.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_syncronizer.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_adapter.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_arbiter_one_hot_arch.vhd
add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/sdpram_model.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/sorting_network.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_components.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_compare.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_pipeline_register.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/oddeven_mergesort_network.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/sorting_network_core.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_queue.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_node.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_fifo.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_reducer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface_components.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_intake_fifo.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_stream_intake.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_tree.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_drop_none.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface_controller.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_axi_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_axi_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_core.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/util.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/reader.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/sync.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/vocal.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_types.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/core.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_core.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_channel_player.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_master_player.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_models.vhd
add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/marchal.vhd
add_vhdl_file sim_1     WORK ../../../src/test/vhdl/argsort_axi_test_bench.vhd

Create Project

この add_files.tcl を create_project.tcl を使って Vivado のプロジェクトを作る際に、読み込ませます。

Merge_Sorter/sim/vivado/argsort_axi/create_project.tcl

  :
proc add_vhdl_file {fileset library_name file_name} {
    set file    [file normalize $file_name]
    set fileset [get_filesets   $fileset  ] 
    add_files -norecurse -fileset $fileset $file
    set file_obj [get_files -of_objects $fileset $file]
    set_property "file_type" "VHDL"        $file_obj
    set_property "library"   $library_name $file_obj
}
source "add_files.tcl"
  :

Vivado > Tools > Run Tcl scripts... > Merge_Sorter/sim/vivado/argsort_axi/create_project.tcl

Tcl Console log （ちょっと長いので折り畳み)

Tcl Console

#-----------------------------------------------------------
# Vivado v2025.1 (64-bit)
# SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
# Start of session at: Fri Dec 19 15:54:19 2025
# Process ID         : 134939
# Current directory  : /home/eda/xilinx/2025.1/Vivado
# Command line       : vivado
# Log file           : /home/eda/xilinx/2025.1/Vivado/vivado.log
# Journal file       : /home/eda/xilinx/2025.1/Vivado/vivado.jou
# Running On         : Tiamat
# Platform           : Ubuntu
# Operating System   : Ubuntu 24.04.3 LTS
# Processor Detail   : AMD Ryzen 5 9600 6-Core Processor
# CPU Frequency      : 3792.792 MHz
# CPU Physical cores : 6
# CPU Logical cores  : 12
# Host memory        : 32393 MB
# Swap memory        : 8589 MB
# Total Virtual      : 40983 MB
# Available Virtual  : 40178 MB
#-----------------------------------------------------------
start_gui
source /home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/create_project.tcl
# set project_directory       [file dirname [info script]]
# set project_name            "argsort_axi"
# set device_parts            "xc7z020clg400-1"
# set test_bench              "ArgSort_AXI_Test_Bench_X04_W1_F1"
# set scenario_file           [file join $project_directory ".." ".." ".." "src" "test" "scenarios" $project_name "test_1.snr" ]
# cd $project_directory
# create_project -force $project_name $project_directory
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/eda/xilinx/2025.1/Vivado/data/ip'.
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 9965.121 ; gain = 194.234 ; free physical = 27676 ; free virtual = 37503
# set_property "part"               $device_parts    [get_projects $project_name]
# set_property "default_lib"        "xil_defaultlib" [get_projects $project_name]
# set_property "simulator_language" "Mixed"          [get_projects $project_name]
# set_property "target_language"    "VHDL"           [get_projects $project_name]
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#     create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#     create_fileset -constrset constrs_1
# }
# if {[string equal [get_filesets -quiet sim_1] ""]} {
#     create_fileset -simset sim_1
# }
# if {[string equal [get_runs -quiet synth_1] ""]} {
#     create_run -name synth_1 -part $device_parts -flow "Vivado Synthesis 2015" -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   # set_property flow     "Vivado Synthesis 2014"     [get_runs synth_1]
#     set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#     set_property strategy "Flow_PerfOptimized_High"   [get_runs synth_1]
# }
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#     create_run -name impl_1 -part $device_parts -flow "Vivado Implementation 2015" -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   # set_property flow     "Vivado Implementation 2014"     [get_runs impl_1]
#     set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#     set_property strategy "Performance_Explore"            [get_runs impl_1]
# }
# current_run -implementation [get_runs impl_1]
# proc add_vhdl_file {fileset library_name file_name} {
#     set file    [file normalize $file_name]
#     set fileset [get_filesets   $fileset  ] 
#     add_files -norecurse -fileset $fileset $file
#     set file_obj [get_files -of_objects $fileset $file]
#     set_property "file_type" "VHDL"        $file_obj
#     set_property "library"   $library_name $file_obj
# }
# source "add_files.tcl"
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/components.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_intake_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_outlet_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pipeline_register_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_types.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/count_down_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/count_up_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/delay_adjuster.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/delay_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_intake_manifold_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_outlet_manifold_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/justifier.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pipeline_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/reducer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/syncronizer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/syncronizer_input_pending_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_components.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_control_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_components.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_data_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/chopper.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pool_intake_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pool_outlet_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_controller_intake_side.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_controller_outlet_side.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_flow_syncronizer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_data_outlet_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_address_channel_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_transfer_queue.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_arbiter.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_receiver.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/sdpram.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_stream_intake_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_stream_outlet_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_read_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_write_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_tree_arbiter.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_read_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_write_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_decoder.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_syncronizer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_adapter.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_arbiter_integer_arch.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/sdpram_model.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/sorting_network.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_components.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_compare.vhd
CRITICAL WARNING: [Vivado 12-3645] Please note that adding or importing multiple files, one at a time, can be performance intensive.  Both add_files and import_files commands accept multiple files as input, and passing a collection of multiple files to a single add_files or import_files commands can offer significant performance improvement.
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_pipeline_register.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/oddeven_mergesort_network.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/sorting_network_core.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_queue.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_node.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_fifo.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_reducer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface_components.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_intake_fifo.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_stream_intake.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_tree.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_drop_none.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface_controller.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_axi_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_axi_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_core.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/util.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/reader.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/sync.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/vocal.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_types.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/core.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_core.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_channel_player.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_master_player.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_models.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/marchal.vhd
## add_vhdl_file sim_1     WORK ../../../src/test/vhdl/argsort_axi_test_bench.vhd
# add_files -fileset constrs_1 -norecurse ./timing.xdc
# update_compile_order -fileset sources_1
# set obj [get_filesets sources_1]
# set_property "top" "ArgSort_AXI"  $obj
# set current_vivado_version [version -short]
# if       { [string first "2025.1" $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".."      $scenario_file ]
# } elseif { [string first "2019.2" $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".."      $scenario_file ]
# } elseif { [string first "2018.3" $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".."      $scenario_file ]
# } elseif { [string first "2017"   $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".." ".." $scenario_file ]
# } else {
#    puts ""
#    puts "ERROR: This model can not run in Vivado <$current_vivado_version>"
#    return 1
# }
# update_compile_order -fileset sim_1
# set obj [get_filesets sim_1]
# set_property "top"     $test_bench [get_filesets sim_1]
# set_property "generic" "SCENARIO_FILE=$scenario_full_path FINISH_ABORT=true" $obj
update_compile_order -fileset sources_1

Run Simulation

Vivado > Flow Navicator > Simulation > Run Simulation > Run Behavioral Simulation

Tcl Console log （ちょっと長いので折り畳み)

Tcl Console

launch_simulation
Command: launch_simulation 
INFO: [Vivado 12-12493] Simulation top is 'ArgSort_AXI_Test_Bench_X04_W1_F1'
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/home/eda/xilinx/2025.1/Vivado/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'ArgSort_AXI_Test_Bench_X04_W1_F1' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj ArgSort_AXI_Test_Bench_X04_W1_F1_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/sorting_network.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/core_components.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/interface.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_types.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_components.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/components.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/interface_components.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Interface'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_types.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/util.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/reader.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/vocal.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/sync.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'SYNC_SIG_DRIVER'
INFO: [VRFC 10-3107] analyzing entity 'SYNC_LOCAL_HUB'
INFO: [VRFC 10-3107] analyzing entity 'SYNC_PRINT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/core.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_models.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_components.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_core.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_channel_player.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'AXI4_CHANNEL_PLAYER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_data_outlet_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_DATA_OUTLET_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_data_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_DATA_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_address_channel_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_ADDRESS_CHANNEL_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_master_player.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_PLAYER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_read_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_READ_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_transfer_queue.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_TRANSFER_QUEUE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_write_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_WRITE_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MEMORY_PLAYER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_register_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_REGISTER_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_register_read_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_REGISTER_READ_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_register_write_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_REGISTER_WRITE_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/chopper.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'CHOPPER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/core_intake_fifo.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Core_Intake_Fifo'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/oddeven_mergesort_network.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/core_stream_intake.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Core_Stream_Intake'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/count_down_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'COUNT_DOWN_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/count_up_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'COUNT_UP_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/delay_adjuster.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'DELAY_ADJUSTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/delay_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'DELAY_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_intake_manifold_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_INTAKE_MANIFOLD_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_intake_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_INTAKE_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_outlet_manifold_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_OUTLET_MANIFOLD_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_outlet_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_OUTLET_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/interface_controller.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Interface_Controller'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/justifier.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'JUSTIFIER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/marchal.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'MARCHAL'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_axi_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_AXI_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_axi_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_AXI_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/merge_sorter_core.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Sorter_Core'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/merge_sorter_node.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Sorter_Node'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/merge_sorter_tree.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Sorter_Tree'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pipeline_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PIPELINE_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pipeline_register_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PIPELINE_REGISTER_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pool_intake_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'POOL_INTAKE_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pool_outlet_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'POOL_OUTLET_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_control_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_CONTROL_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_controller_intake_side.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_CONTROLLER_INTAKE_SIDE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_controller_outlet_side.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_CONTROLLER_OUTLET_SIDE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_flow_syncronizer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_FLOW_SYNCRONIZER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_stream_intake_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_STREAM_INTAKE_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_stream_outlet_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_STREAM_OUTLET_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_arbiter.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_ARBITER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_arbiter_integer_arch.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_receiver.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_RECEIVER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_tree_arbiter.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_TREE_ARBITER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/reducer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REDUCER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/register_access_adapter.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REGISTER_ACCESS_ADAPTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/register_access_decoder.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REGISTER_ACCESS_DECODER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/register_access_syncronizer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REGISTER_ACCESS_SYNCRONIZER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/sdpram.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'SDPRAM'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/sdpram_model.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/sorting_network_core.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Sorting_Network_Core'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/syncronizer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'SYNCRONIZER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/syncronizer_input_pending_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'SYNCRONIZER_INPUT_PENDING_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_compare.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Compare'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_drop_none.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Drop_None'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_fifo.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Fifo'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_pipeline_register.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Pipeline_Register'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_queue.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Queue'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_reducer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Reducer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/test/vhdl/argsort_axi_test_bench.vhd" into library WORK
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W1_F0'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W1_F1'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W1_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W2_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X16_W1_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X16_W2_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X16_W2_F0'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X32_W1_F2'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -generic_top SCENARIO_FILE=/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/../../../src/test/scenarios/argsort_axi/test_1.snr -generic_top FINISH_ABORT=true -L MERGE_SORTER -L PIPEWORK -L DUMMY_PLUG -L WORK -L secureip --snapshot ArgSort_AXI_Test_Bench_X04_W1_F1_behav WORK.ArgSort_AXI_Test_Bench_X04_W1_F1 -log elaborate.log
Vivado Simulator v2025.1.0
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /home/eda/xilinx/2025.1/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -generic_top SCENARIO_FILE=/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/../../../src/test/scenarios/argsort_axi/test_1.snr -generic_top FINISH_ABORT=true -L MERGE_SORTER -L PIPEWORK -L DUMMY_PLUG -L WORK -L secureip --snapshot ArgSort_AXI_Test_Bench_X04_W1_F1_behav WORK.ArgSort_AXI_Test_Bench_X04_W1_F1 -log elaborate.log 
Using 8 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by AMD, however they may be appropriate for your system, so the flow will attempt to continue.  If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
    LIBRARY_PATH
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package merge_sorter.interface
Compiling package ieee.numeric_std
Compiling package merge_sorter.argsort_axi_components
Compiling package dummy_plug.axi4_types
Compiling package dummy_plug.reader
Compiling package dummy_plug.util
Compiling package dummy_plug.vocal
Compiling package dummy_plug.sync
Compiling package dummy_plug.core
Compiling package dummy_plug.axi4_models
Compiling package merge_sorter.word
Compiling package merge_sorter.sorting_network
Compiling package merge_sorter.core_components
Compiling package pipework.axi4_types
Compiling package pipework.axi4_components
Compiling package pipework.components
Compiling package merge_sorter.interface_components
Compiling package pipework.pump_components
Compiling package merge_sorter.oddeven_mergesort_network
Compiling package dummy_plug.axi4_core
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=2,max_piece=2...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=0,dat...]
Compiling architecture rtl of entity pipework.AXI4_DATA_PORT [\AXI4_DATA_PORT(addr_bits=7,size...]
Compiling architecture rtl of entity pipework.AXI4_DATA_OUTLET_PORT [\AXI4_DATA_OUTLET_PORT(tran_addr...]
Compiling architecture rtl of entity pipework.AXI4_REGISTER_READ_INTERFACE [\AXI4_REGISTER_READ_INTERFACE(re...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(words=4)\]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(i_width=4,o_width=4,o_s...]
Compiling architecture rtl of entity pipework.AXI4_REGISTER_WRITE_INTERFACE [\AXI4_REGISTER_WRITE_INTERFACE(r...]
Compiling architecture integer_arch of entity pipework.QUEUE_ARBITER [\QUEUE_ARBITER(max_num=1)\]
Compiling architecture rtl of entity pipework.AXI4_REGISTER_INTERFACE [\AXI4_REGISTER_INTERFACE(regs_ad...]
Compiling architecture rtl of entity pipework.SYNCRONIZER_INPUT_PENDING_REGISTER [\SYNCRONIZER_INPUT_PENDING_REGIS...]
Compiling architecture rtl of entity pipework.SYNCRONIZER_INPUT_PENDING_REGISTER [\SYNCRONIZER_INPUT_PENDING_REGIS...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=44,i_clk_...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=32,val_bi...]
Compiling architecture rtl of entity pipework.REGISTER_ACCESS_SYNCRONIZER [\REGISTER_ACCESS_SYNCRONIZER(add...]
Compiling architecture rtl of entity pipework.REGISTER_ACCESS_DECODER [\REGISTER_ACCESS_DECODER(addr_wi...]
Compiling architecture rtl of entity pipework.REGISTER_ACCESS_ADAPTER [\REGISTER_ACCESS_ADAPTER(addr_wi...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=11,max_piece=...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_ADDRESS_CHANNEL_CONTROLLER [\AXI4_MASTER_ADDRESS_CHANNEL_CON...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_TRANSFER_QUEUE [\AXI4_MASTER_TRANSFER_QUEUE(size...]
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=3,max_piece=3...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=32,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_READ_INTERFACE [\AXI4_MASTER_READ_INTERFACE(axi4...]
Compiling architecture rtl of entity pipework.SYNCRONIZER_INPUT_PENDING_REGISTER [\SYNCRONIZER_INPUT_PENDING_REGIS...]
Compiling architecture rtl of entity pipework.DELAY_REGISTER [\DELAY_REGISTER(data_bits=14,del...]
Compiling architecture rtl of entity pipework.DELAY_ADJUSTER [\DELAY_ADJUSTER(data_bits=1,dela...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=20,val_bi...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(event_siz...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=17,val_bi...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(xfer_size...]
Compiling architecture rtl of entity pipework.FLOAT_OUTLET_VALVE [\FLOAT_OUTLET_VALVE(count_bits=1...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=32,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.COUNT_UP_REGISTER [\COUNT_UP_REGISTER(regs_bits=64)...]
Compiling architecture rtl of entity pipework.COUNT_DOWN_REGISTER [\COUNT_DOWN_REGISTER(12,0)(31,0)...]
Compiling architecture rtl of entity pipework.COUNT_UP_REGISTER [\COUNT_UP_REGISTER(bits=12,regs_...]
Compiling architecture rtl of entity pipework.PUMP_CONTROL_REGISTER [\PUMP_CONTROL_REGISTER(mode_bits...]
Compiling architecture rtl of entity pipework.FLOAT_INTAKE_VALVE [\FLOAT_INTAKE_VALVE(count_bits=1...]
Compiling architecture rtl of entity pipework.FLOAT_INTAKE_MANIFOLD_VALVE [\FLOAT_INTAKE_MANIFOLD_VALVE(fix...]
Compiling architecture rtl of entity pipework.PUMP_CONTROLLER_INTAKE_SIDE [\PUMP_CONTROLLER_INTAKE_SIDE(reg...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_INTAKE_CONTROLLER [\PUMP_STREAM_INTAKE_CONTROLLER(i...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.ArgSort_Reader [\ArgSort_Reader(reg_param=(128,0...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI_Reader [\ArgSort_AXI_Reader(axi_id_width...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_TRANSFER_QUEUE [\AXI4_MASTER_TRANSFER_QUEUE(size...]
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=3,max_piece=3...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=0,dat...]
Compiling architecture rtl of entity pipework.AXI4_DATA_PORT [\AXI4_DATA_PORT(data_bits=64,siz...]
Compiling architecture rtl of entity pipework.AXI4_DATA_OUTLET_PORT [\AXI4_DATA_OUTLET_PORT(port_data...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_WRITE_INTERFACE [\AXI4_MASTER_WRITE_INTERFACE(axi...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(event_siz...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(xfer_size...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=32,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.FLOAT_OUTLET_MANIFOLD_VALVE [\FLOAT_OUTLET_MANIFOLD_VALVE(fix...]
Compiling architecture rtl of entity pipework.PUMP_CONTROLLER_OUTLET_SIDE [\PUMP_CONTROLLER_OUTLET_SIDE(reg...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_OUTLET_CONTROLLER [\PUMP_STREAM_OUTLET_CONTROLLER(o...]
Compiling architecture rtl of entity merge_sorter.ArgSort_Writer [\ArgSort_Writer(reg_param=(128,0...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI_Writer [\ArgSort_AXI_Writer(axi_id_width...]
Compiling architecture integer_arch of entity pipework.QUEUE_ARBITER [\QUEUE_ARBITER(max_num=3)\]
Compiling architecture rtl of entity pipework.QUEUE_TREE_ARBITER [\QUEUE_TREE_ARBITER(max_num=3,no...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=64,strb_bit...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_INTAKE_CONTROLLER [\PUMP_STREAM_INTAKE_CONTROLLER(i...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(reg_param=(128,0,0...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(channel=1,reg_para...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(channel=2,reg_para...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(channel=3,reg_para...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_ADDRESS_CHANNEL_CONTROLLER [\AXI4_MASTER_ADDRESS_CHANNEL_CON...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_TRANSFER_QUEUE [\AXI4_MASTER_TRANSFER_QUEUE(sel_...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=64,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=64,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_READ_INTERFACE [\AXI4_MASTER_READ_INTERFACE(axi4...]
Compiling architecture rtl of entity merge_sorter.Merge_AXI_Reader [\Merge_AXI_Reader(ways=4,axi_id_...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity pipework.AXI4_DATA_PORT [\AXI4_DATA_PORT(data_bits=64,siz...]
Compiling architecture rtl of entity pipework.AXI4_DATA_OUTLET_PORT [\AXI4_DATA_OUTLET_PORT(port_data...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_WRITE_INTERFACE [\AXI4_MASTER_WRITE_INTERFACE(axi...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_OUTLET_CONTROLLER [\PUMP_STREAM_OUTLET_CONTROLLER(o...]
Compiling architecture rtl of entity merge_sorter.Merge_Writer [\Merge_Writer(reg_param=(128,0,0...]
Compiling architecture rtl of entity merge_sorter.Merge_AXI_Writer [\Merge_AXI_Writer(axi_id_base=2,...]
Compiling architecture rtl of entity merge_sorter.Interface_Controller [\Interface_Controller(ways=4,wor...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI_Interface [\ArgSort_AXI_Interface(ways=4,mr...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=68,o_width=4,...]
Compiling architecture rtl of entity merge_sorter.Word_Reducer [\Word_Reducer(word_param=(67,64,...]
Compiling architecture rtl of entity merge_sorter.Core_Stream_Intake [\Core_Stream_Intake(word_param=(...]
Compiling architecture rtl of entity merge_sorter.Word_Fifo [\Word_Fifo(word_param=(67,64,0,6...]
Compiling architecture rtl of entity merge_sorter.Core_Intake_Fifo [\Core_Intake_Fifo(word_param=(67...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity merge_sorter.Word_Queue [\Word_Queue(word_param=(67,64,0,...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Tree [\Merge_Sorter_Tree(word_param=(6...]
Compiling architecture rtl of entity merge_sorter.Word_Compare [\Word_Compare(word_param=(67,64,...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Node [\Merge_Sorter_Node(word_param=(6...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Tree [\Merge_Sorter_Tree(word_param=(6...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Tree [\Merge_Sorter_Tree(word_param=(6...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=68,queue_size...]
Compiling architecture rtl of entity merge_sorter.Word_Reducer [\Word_Reducer(word_param=(67,64,...]
Compiling architecture rtl of entity merge_sorter.Word_Drop_None [\Word_Drop_None(word_param=(67,6...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Core [\Merge_Sorter_Core(mrg_ways=4,mr...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI [\ArgSort_AXI(comp_sign=true,mrg_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MARCHAL:S...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MARCHAL:S...]
Compiling architecture model of entity dummy_plug.MARCHAL [\MARCHAL(scenario_file="/home/ic...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC(...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC(...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_LOCAL_HUB [\SYNC_LOCAL_HUB(name="CSR:SYNC_L...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_LOCAL_HUB [\SYNC_LOCAL_HUB(name="CSR:SYNC_T...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_LOCAL_HUB [\SYNC_LOCAL_HUB(name="CSR:SYNC_T...]
Compiling architecture model of entity dummy_plug.AXI4_MASTER_PLAYER [\AXI4_MASTER_PLAYER(scenario_fil...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="STM:SYNC(...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="STM:SYNC(...]
Compiling architecture model of entity dummy_plug.AXI4_MEMORY_PLAYER [\AXI4_MEMORY_PLAYER(scenario_fil...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MRG:SYNC(...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MRG:SYNC(...]
Compiling architecture model of entity dummy_plug.AXI4_MEMORY_PLAYER [\AXI4_MEMORY_PLAYER(scenario_fil...]
Compiling architecture model of entity work.ArgSort_AXI_Test_Bench [\ArgSort_AXI_Test_Bench(name="TE...]
Compiling architecture model of entity work.argsort_axi_test_bench_x04_w1_f1
Built simulation snapshot ArgSort_AXI_Test_Bench_X04_W1_F1_behav
execute_script: Time (s): cpu = 00:02:24 ; elapsed = 00:02:01 . Memory (MB): peak = 10002.934 ; gain = 10.000 ; free physical = 27553 ; free virtual = 37416
INFO: [USF-XSim-69] 'elaborate' step finished in '122' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "ArgSort_AXI_Test_Bench_X04_W1_F1_behav -key {Behavioral:sim_1:Functional:ArgSort_AXI_Test_Bench_X04_W1_F1} -tclbatch {ArgSort_AXI_Test_Bench_X04_W1_F1.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source ArgSort_AXI_Test_Bench_X04_W1_F1.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
        35 ns| MARCHAL < ArgSort_AXI_Test TEST 1 Start.
        55 ns| MARCHAL < ArgSort_AXI_Test TEST 1.1 Start.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'ArgSort_AXI_Test_Bench_X04_W1_F1_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:02:30 ; elapsed = 00:02:06 . Memory (MB): peak = 10093.055 ; gain = 109.695 ; free physical = 27493 ; free virtual = 37359
set_property -name {xsim.simulate.runtime} -value {} -objects [get_filesets sim_1]
set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_project
source /home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/create_project.tcl
# set project_directory       [file dirname [info script]]
# set project_name            "argsort_axi"
# set device_parts            "xc7z020clg400-1"
# set test_bench              "ArgSort_AXI_Test_Bench_X04_W1_F1"
# set scenario_file           [file join $project_directory ".." ".." ".." "src" "test" "scenarios" $project_name "test_1.snr" ]
# cd $project_directory
# create_project -force $project_name $project_directory
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/eda/xilinx/2025.1/Vivado/data/ip'.
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 10093.223 ; gain = 0.000 ; free physical = 27556 ; free virtual = 37385
# set_property "part"               $device_parts    [get_projects $project_name]
# set_property "default_lib"        "xil_defaultlib" [get_projects $project_name]
# set_property "simulator_language" "Mixed"          [get_projects $project_name]
# set_property "target_language"    "VHDL"           [get_projects $project_name]
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#     create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#     create_fileset -constrset constrs_1
# }
# if {[string equal [get_filesets -quiet sim_1] ""]} {
#     create_fileset -simset sim_1
# }
# if {[string equal [get_runs -quiet synth_1] ""]} {
#     create_run -name synth_1 -part $device_parts -flow "Vivado Synthesis 2015" -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   # set_property flow     "Vivado Synthesis 2014"     [get_runs synth_1]
#     set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#     set_property strategy "Flow_PerfOptimized_High"   [get_runs synth_1]
# }
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#     create_run -name impl_1 -part $device_parts -flow "Vivado Implementation 2015" -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   # set_property flow     "Vivado Implementation 2014"     [get_runs impl_1]
#     set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#     set_property strategy "Performance_Explore"            [get_runs impl_1]
# }
# current_run -implementation [get_runs impl_1]
# proc add_vhdl_file {fileset library_name file_name} {
#     set file    [file normalize $file_name]
#     set fileset [get_filesets   $fileset  ] 
#     add_files -norecurse -fileset $fileset $file
#     set file_obj [get_files -of_objects $fileset $file]
#     set_property "file_type" "VHDL"        $file_obj
#     set_property "library"   $library_name $file_obj
# }
# source "add_files.tcl"
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/components.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_intake_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_outlet_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pipeline_register_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_types.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/count_down_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/count_up_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/delay_adjuster.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/delay_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_intake_manifold_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/float_outlet_manifold_valve.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/justifier.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pipeline_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/reducer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/syncronizer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/syncronizer_input_pending_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_components.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_control_register.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_components.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_data_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/chopper.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pool_intake_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/pool_outlet_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_controller_intake_side.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_controller_outlet_side.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_flow_syncronizer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_data_outlet_port.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_address_channel_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_transfer_queue.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_arbiter.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_receiver.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/sdpram.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_stream_intake_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/pump/pump_stream_outlet_controller.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_read_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_master_write_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_tree_arbiter.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_read_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_write_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_decoder.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_syncronizer.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/axi4/axi4_register_interface.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/register_access_adapter.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/queue_arbiter_integer_arch.vhd
## add_vhdl_file sources_1 PIPEWORK ../../../PipeWork/src/components/sdpram_model.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/sorting_network.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_components.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_compare.vhd
CRITICAL WARNING: [Vivado 12-3645] Please note that adding or importing multiple files, one at a time, can be performance intensive.  Both add_files and import_files commands accept multiple files as input, and passing a collection of multiple files to a single add_files or import_files commands can offer significant performance improvement.
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_pipeline_register.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/oddeven_mergesort_network.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/sorting_network_core.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_queue.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_node.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_fifo.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_reducer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface_components.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_intake_fifo.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/core_stream_intake.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_tree.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/word_drop_none.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/interface_controller.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_axi_reader.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/interface/merge_axi_writer.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/core/merge_sorter_core.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd
## add_vhdl_file sources_1 MERGE_SORTER ../../../src/main/vhdl/examples/argsort_axi/argsort_axi.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/util.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/reader.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/sync.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/vocal.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_types.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/core.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_core.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_channel_player.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_master_player.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_models.vhd
## add_vhdl_file sim_1     DUMMY_PLUG ../../../Dummy_Plug/src/main/vhdl/core/marchal.vhd
## add_vhdl_file sim_1     WORK ../../../src/test/vhdl/argsort_axi_test_bench.vhd
# add_files -fileset constrs_1 -norecurse ./timing.xdc
# update_compile_order -fileset sources_1
# set obj [get_filesets sources_1]
# set_property "top" "ArgSort_AXI"  $obj
# set current_vivado_version [version -short]
# if       { [string first "2025.1" $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".."      $scenario_file ]
# } elseif { [string first "2019.2" $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".."      $scenario_file ]
# } elseif { [string first "2018.3" $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".."      $scenario_file ]
# } elseif { [string first "2017"   $current_vivado_version ] == 0 } {
#     set scenario_full_path [file join ".." ".." ".." ".." $scenario_file ]
# } else {
#    puts ""
#    puts "ERROR: This model can not run in Vivado <$current_vivado_version>"
#    return 1
# }
# update_compile_order -fileset sim_1
# set obj [get_filesets sim_1]
# set_property "top"     $test_bench $obj
# set_property "generic" "SCENARIO_FILE=$scenario_full_path FINISH_ABORT=true" $obj
# set_property -name {xsim.simulate.runtime} -value {all} -objects $obj
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation 
INFO: [Vivado 12-12493] Simulation top is 'ArgSort_AXI_Test_Bench_X04_W1_F1'
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/home/eda/xilinx/2025.1/Vivado/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'ArgSort_AXI_Test_Bench_X04_W1_F1' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj ArgSort_AXI_Test_Bench_X04_W1_F1_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/sorting_network.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/core_components.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/interface.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_types.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_components.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/components.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/interface_components.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Interface'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_types.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/util.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/reader.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/vocal.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/sync.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'SYNC_SIG_DRIVER'
INFO: [VRFC 10-3107] analyzing entity 'SYNC_LOCAL_HUB'
INFO: [VRFC 10-3107] analyzing entity 'SYNC_PRINT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/core.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_models.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_components.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/examples/argsort_axi/argsort_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_core.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_channel_player.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'AXI4_CHANNEL_PLAYER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_data_outlet_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_DATA_OUTLET_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_data_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_DATA_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_address_channel_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_ADDRESS_CHANNEL_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_master_player.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_PLAYER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_read_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_READ_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_transfer_queue.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_TRANSFER_QUEUE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_master_write_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MASTER_WRITE_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'AXI4_MEMORY_PLAYER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_register_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_REGISTER_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_register_read_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_REGISTER_READ_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/axi4/axi4_register_write_interface.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'AXI4_REGISTER_WRITE_INTERFACE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/chopper.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'CHOPPER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/core_intake_fifo.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Core_Intake_Fifo'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/oddeven_mergesort_network.vhd" into library MERGE_SORTER
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/core_stream_intake.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Core_Stream_Intake'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/count_down_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'COUNT_DOWN_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/count_up_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'COUNT_UP_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/delay_adjuster.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'DELAY_ADJUSTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/delay_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'DELAY_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_intake_manifold_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_INTAKE_MANIFOLD_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_intake_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_INTAKE_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_outlet_manifold_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_OUTLET_MANIFOLD_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/float_outlet_valve.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'FLOAT_OUTLET_VALVE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/interface_controller.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Interface_Controller'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/justifier.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'JUSTIFIER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/core/marchal.vhd" into library DUMMY_PLUG
INFO: [VRFC 10-3107] analyzing entity 'MARCHAL'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_axi_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_AXI_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_axi_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_AXI_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_reader.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Reader'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/merge_sorter_core.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Sorter_Core'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/merge_sorter_node.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Sorter_Node'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/merge_sorter_tree.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Sorter_Tree'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/interface/merge_writer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Merge_Writer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pipeline_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PIPELINE_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pipeline_register_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PIPELINE_REGISTER_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pool_intake_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'POOL_INTAKE_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/pool_outlet_port.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'POOL_OUTLET_PORT'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_control_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_CONTROL_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_controller_intake_side.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_CONTROLLER_INTAKE_SIDE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_controller_outlet_side.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_CONTROLLER_OUTLET_SIDE'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_flow_syncronizer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_FLOW_SYNCRONIZER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_stream_intake_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_STREAM_INTAKE_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/pump/pump_stream_outlet_controller.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'PUMP_STREAM_OUTLET_CONTROLLER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_arbiter.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_ARBITER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_arbiter_integer_arch.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_receiver.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_RECEIVER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/queue_tree_arbiter.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'QUEUE_TREE_ARBITER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/reducer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REDUCER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/register_access_adapter.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REGISTER_ACCESS_ADAPTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/register_access_decoder.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REGISTER_ACCESS_DECODER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/register_access_syncronizer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'REGISTER_ACCESS_SYNCRONIZER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/sdpram.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'SDPRAM'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/sdpram_model.vhd" into library PIPEWORK
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/sorting_network_core.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Sorting_Network_Core'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/syncronizer.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'SYNCRONIZER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/PipeWork/src/components/syncronizer_input_pending_register.vhd" into library PIPEWORK
INFO: [VRFC 10-3107] analyzing entity 'SYNCRONIZER_INPUT_PENDING_REGISTER'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_compare.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Compare'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_drop_none.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Drop_None'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_fifo.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Fifo'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_pipeline_register.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Pipeline_Register'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_queue.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Queue'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/main/vhdl/core/word_reducer.vhd" into library MERGE_SORTER
INFO: [VRFC 10-3107] analyzing entity 'Word_Reducer'
INFO: [VRFC 10-163] Analyzing VHDL file "/home/ichiro/tmp/Merge_Sorter/src/test/vhdl/argsort_axi_test_bench.vhd" into library WORK
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W1_F0'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W1_F1'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W1_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X04_W2_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X16_W1_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X16_W2_F2'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X16_W2_F0'
INFO: [VRFC 10-3107] analyzing entity 'ArgSort_AXI_Test_Bench_X32_W1_F2'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -generic_top SCENARIO_FILE=/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/../../../src/test/scenarios/argsort_axi/test_1.snr -generic_top FINISH_ABORT=true -L MERGE_SORTER -L PIPEWORK -L DUMMY_PLUG -L WORK -L secureip --snapshot ArgSort_AXI_Test_Bench_X04_W1_F1_behav WORK.ArgSort_AXI_Test_Bench_X04_W1_F1 -log elaborate.log
Vivado Simulator v2025.1.0
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /home/eda/xilinx/2025.1/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -generic_top SCENARIO_FILE=/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/../../../src/test/scenarios/argsort_axi/test_1.snr -generic_top FINISH_ABORT=true -L MERGE_SORTER -L PIPEWORK -L DUMMY_PLUG -L WORK -L secureip --snapshot ArgSort_AXI_Test_Bench_X04_W1_F1_behav WORK.ArgSort_AXI_Test_Bench_X04_W1_F1 -log elaborate.log 
Using 8 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by AMD, however they may be appropriate for your system, so the flow will attempt to continue.  If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
    LIBRARY_PATH
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package merge_sorter.interface
Compiling package ieee.numeric_std
Compiling package merge_sorter.argsort_axi_components
Compiling package dummy_plug.axi4_types
Compiling package dummy_plug.reader
Compiling package dummy_plug.util
Compiling package dummy_plug.vocal
Compiling package dummy_plug.sync
Compiling package dummy_plug.core
Compiling package dummy_plug.axi4_models
Compiling package merge_sorter.word
Compiling package merge_sorter.sorting_network
Compiling package merge_sorter.core_components
Compiling package pipework.axi4_types
Compiling package pipework.axi4_components
Compiling package pipework.components
Compiling package merge_sorter.interface_components
Compiling package pipework.pump_components
Compiling package merge_sorter.oddeven_mergesort_network
Compiling package dummy_plug.axi4_core
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=2,max_piece=2...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=0,dat...]
Compiling architecture rtl of entity pipework.AXI4_DATA_PORT [\AXI4_DATA_PORT(addr_bits=7,size...]
Compiling architecture rtl of entity pipework.AXI4_DATA_OUTLET_PORT [\AXI4_DATA_OUTLET_PORT(tran_addr...]
Compiling architecture rtl of entity pipework.AXI4_REGISTER_READ_INTERFACE [\AXI4_REGISTER_READ_INTERFACE(re...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(words=4)\]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(i_width=4,o_width=4,o_s...]
Compiling architecture rtl of entity pipework.AXI4_REGISTER_WRITE_INTERFACE [\AXI4_REGISTER_WRITE_INTERFACE(r...]
Compiling architecture integer_arch of entity pipework.QUEUE_ARBITER [\QUEUE_ARBITER(max_num=1)\]
Compiling architecture rtl of entity pipework.AXI4_REGISTER_INTERFACE [\AXI4_REGISTER_INTERFACE(regs_ad...]
Compiling architecture rtl of entity pipework.SYNCRONIZER_INPUT_PENDING_REGISTER [\SYNCRONIZER_INPUT_PENDING_REGIS...]
Compiling architecture rtl of entity pipework.SYNCRONIZER_INPUT_PENDING_REGISTER [\SYNCRONIZER_INPUT_PENDING_REGIS...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=44,i_clk_...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=32,val_bi...]
Compiling architecture rtl of entity pipework.REGISTER_ACCESS_SYNCRONIZER [\REGISTER_ACCESS_SYNCRONIZER(add...]
Compiling architecture rtl of entity pipework.REGISTER_ACCESS_DECODER [\REGISTER_ACCESS_DECODER(addr_wi...]
Compiling architecture rtl of entity pipework.REGISTER_ACCESS_ADAPTER [\REGISTER_ACCESS_ADAPTER(addr_wi...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=11,max_piece=...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_ADDRESS_CHANNEL_CONTROLLER [\AXI4_MASTER_ADDRESS_CHANNEL_CON...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_TRANSFER_QUEUE [\AXI4_MASTER_TRANSFER_QUEUE(size...]
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=3,max_piece=3...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=32,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_READ_INTERFACE [\AXI4_MASTER_READ_INTERFACE(axi4...]
Compiling architecture rtl of entity pipework.SYNCRONIZER_INPUT_PENDING_REGISTER [\SYNCRONIZER_INPUT_PENDING_REGIS...]
Compiling architecture rtl of entity pipework.DELAY_REGISTER [\DELAY_REGISTER(data_bits=14,del...]
Compiling architecture rtl of entity pipework.DELAY_ADJUSTER [\DELAY_ADJUSTER(data_bits=1,dela...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=20,val_bi...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(event_siz...]
Compiling architecture rtl of entity pipework.SYNCRONIZER [\SYNCRONIZER(data_bits=17,val_bi...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(xfer_size...]
Compiling architecture rtl of entity pipework.FLOAT_OUTLET_VALVE [\FLOAT_OUTLET_VALVE(count_bits=1...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=32,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.COUNT_UP_REGISTER [\COUNT_UP_REGISTER(regs_bits=64)...]
Compiling architecture rtl of entity pipework.COUNT_DOWN_REGISTER [\COUNT_DOWN_REGISTER(12,0)(31,0)...]
Compiling architecture rtl of entity pipework.COUNT_UP_REGISTER [\COUNT_UP_REGISTER(bits=12,regs_...]
Compiling architecture rtl of entity pipework.PUMP_CONTROL_REGISTER [\PUMP_CONTROL_REGISTER(mode_bits...]
Compiling architecture rtl of entity pipework.FLOAT_INTAKE_VALVE [\FLOAT_INTAKE_VALVE(count_bits=1...]
Compiling architecture rtl of entity pipework.FLOAT_INTAKE_MANIFOLD_VALVE [\FLOAT_INTAKE_MANIFOLD_VALVE(fix...]
Compiling architecture rtl of entity pipework.PUMP_CONTROLLER_INTAKE_SIDE [\PUMP_CONTROLLER_INTAKE_SIDE(reg...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_INTAKE_CONTROLLER [\PUMP_STREAM_INTAKE_CONTROLLER(i...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.ArgSort_Reader [\ArgSort_Reader(reg_param=(128,0...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI_Reader [\ArgSort_AXI_Reader(axi_id_width...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_TRANSFER_QUEUE [\AXI4_MASTER_TRANSFER_QUEUE(size...]
Compiling architecture rtl of entity pipework.CHOPPER [\CHOPPER(min_piece=3,max_piece=3...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=0,dat...]
Compiling architecture rtl of entity pipework.AXI4_DATA_PORT [\AXI4_DATA_PORT(data_bits=64,siz...]
Compiling architecture rtl of entity pipework.AXI4_DATA_OUTLET_PORT [\AXI4_DATA_OUTLET_PORT(port_data...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_WRITE_INTERFACE [\AXI4_MASTER_WRITE_INTERFACE(axi...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(event_siz...]
Compiling architecture rtl of entity pipework.PUMP_FLOW_SYNCRONIZER [\PUMP_FLOW_SYNCRONIZER(xfer_size...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=32,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=32,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=32,p...]
Compiling architecture rtl of entity pipework.FLOAT_OUTLET_MANIFOLD_VALVE [\FLOAT_OUTLET_MANIFOLD_VALVE(fix...]
Compiling architecture rtl of entity pipework.PUMP_CONTROLLER_OUTLET_SIDE [\PUMP_CONTROLLER_OUTLET_SIDE(reg...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_OUTLET_CONTROLLER [\PUMP_STREAM_OUTLET_CONTROLLER(o...]
Compiling architecture rtl of entity merge_sorter.ArgSort_Writer [\ArgSort_Writer(reg_param=(128,0...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI_Writer [\ArgSort_AXI_Writer(axi_id_width...]
Compiling architecture integer_arch of entity pipework.QUEUE_ARBITER [\QUEUE_ARBITER(max_num=3)\]
Compiling architecture rtl of entity pipework.QUEUE_TREE_ARBITER [\QUEUE_TREE_ARBITER(max_num=3,no...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=64,strb_bit...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_INTAKE_CONTROLLER [\PUMP_STREAM_INTAKE_CONTROLLER(i...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(reg_param=(128,0,0...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(channel=1,reg_para...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(channel=2,reg_para...]
Compiling architecture model of entity pipework.SDPRAM [\SDPRAM(depth=15,rwidth=6,webit=...]
Compiling architecture rtl of entity merge_sorter.Merge_Reader [\Merge_Reader(channel=3,reg_para...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_ADDRESS_CHANNEL_CONTROLLER [\AXI4_MASTER_ADDRESS_CHANNEL_CON...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_TRANSFER_QUEUE [\AXI4_MASTER_TRANSFER_QUEUE(sel_...]
Compiling architecture rtl of entity pipework.JUSTIFIER [\JUSTIFIER(word_bits=64,strb_bit...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=64,strb_bits=...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_READ_INTERFACE [\AXI4_MASTER_READ_INTERFACE(axi4...]
Compiling architecture rtl of entity merge_sorter.Merge_AXI_Reader [\Merge_AXI_Reader(ways=4,axi_id_...]
Compiling architecture rtl of entity pipework.POOL_OUTLET_PORT [\POOL_OUTLET_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity pipework.AXI4_DATA_PORT [\AXI4_DATA_PORT(data_bits=64,siz...]
Compiling architecture rtl of entity pipework.AXI4_DATA_OUTLET_PORT [\AXI4_DATA_OUTLET_PORT(port_data...]
Compiling architecture rtl of entity pipework.AXI4_MASTER_WRITE_INTERFACE [\AXI4_MASTER_WRITE_INTERFACE(axi...]
Compiling architecture rtl of entity pipework.POOL_INTAKE_PORT [\POOL_INTAKE_PORT(word_bits=64,p...]
Compiling architecture rtl of entity pipework.PUMP_STREAM_OUTLET_CONTROLLER [\PUMP_STREAM_OUTLET_CONTROLLER(o...]
Compiling architecture rtl of entity merge_sorter.Merge_Writer [\Merge_Writer(reg_param=(128,0,0...]
Compiling architecture rtl of entity merge_sorter.Merge_AXI_Writer [\Merge_AXI_Writer(axi_id_base=2,...]
Compiling architecture rtl of entity merge_sorter.Interface_Controller [\Interface_Controller(ways=4,wor...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI_Interface [\ArgSort_AXI_Interface(ways=4,mr...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=68,o_width=4,...]
Compiling architecture rtl of entity merge_sorter.Word_Reducer [\Word_Reducer(word_param=(67,64,...]
Compiling architecture rtl of entity merge_sorter.Core_Stream_Intake [\Core_Stream_Intake(word_param=(...]
Compiling architecture rtl of entity merge_sorter.Word_Fifo [\Word_Fifo(word_param=(67,64,0,6...]
Compiling architecture rtl of entity merge_sorter.Core_Intake_Fifo [\Core_Intake_Fifo(word_param=(67...]
Compiling architecture rtl of entity pipework.QUEUE_REGISTER [\QUEUE_REGISTER(queue_size=2,dat...]
Compiling architecture rtl of entity merge_sorter.Word_Queue [\Word_Queue(word_param=(67,64,0,...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Tree [\Merge_Sorter_Tree(word_param=(6...]
Compiling architecture rtl of entity merge_sorter.Word_Compare [\Word_Compare(word_param=(67,64,...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Node [\Merge_Sorter_Node(word_param=(6...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Tree [\Merge_Sorter_Tree(word_param=(6...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Tree [\Merge_Sorter_Tree(word_param=(6...]
Compiling architecture rtl of entity pipework.REDUCER [\REDUCER(word_bits=68,queue_size...]
Compiling architecture rtl of entity merge_sorter.Word_Reducer [\Word_Reducer(word_param=(67,64,...]
Compiling architecture rtl of entity merge_sorter.Word_Drop_None [\Word_Drop_None(word_param=(67,6...]
Compiling architecture rtl of entity merge_sorter.Merge_Sorter_Core [\Merge_Sorter_Core(mrg_ways=4,mr...]
Compiling architecture rtl of entity merge_sorter.ArgSort_AXI [\ArgSort_AXI(comp_sign=true,mrg_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MARCHAL:S...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MARCHAL:S...]
Compiling architecture model of entity dummy_plug.MARCHAL [\MARCHAL(scenario_file="/home/ic...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC(...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC(...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.AXI4_CHANNEL_PLAYER [\AXI4_CHANNEL_PLAYER(scenario_fi...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_LOCAL_HUB [\SYNC_LOCAL_HUB(name="CSR:SYNC_L...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_LOCAL_HUB [\SYNC_LOCAL_HUB(name="CSR:SYNC_T...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="CSR:SYNC_...]
Compiling architecture model of entity dummy_plug.SYNC_LOCAL_HUB [\SYNC_LOCAL_HUB(name="CSR:SYNC_T...]
Compiling architecture model of entity dummy_plug.AXI4_MASTER_PLAYER [\AXI4_MASTER_PLAYER(scenario_fil...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="STM:SYNC(...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="STM:SYNC(...]
Compiling architecture model of entity dummy_plug.AXI4_MEMORY_PLAYER [\AXI4_MEMORY_PLAYER(scenario_fil...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MRG:SYNC(...]
Compiling architecture model of entity dummy_plug.SYNC_SIG_DRIVER [\SYNC_SIG_DRIVER(name="MRG:SYNC(...]
Compiling architecture model of entity dummy_plug.AXI4_MEMORY_PLAYER [\AXI4_MEMORY_PLAYER(scenario_fil...]
Compiling architecture model of entity work.ArgSort_AXI_Test_Bench [\ArgSort_AXI_Test_Bench(name="TE...]
Compiling architecture model of entity work.argsort_axi_test_bench_x04_w1_f1
Built simulation snapshot ArgSort_AXI_Test_Bench_X04_W1_F1_behav
execute_script: Time (s): cpu = 00:02:27 ; elapsed = 00:02:04 . Memory (MB): peak = 10093.223 ; gain = 0.000 ; free physical = 27505 ; free virtual = 37369
INFO: [USF-XSim-69] 'elaborate' step finished in '124' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/ichiro/tmp/Merge_Sorter/sim/vivado/argsort_axi/argsort_axi.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "ArgSort_AXI_Test_Bench_X04_W1_F1_behav -key {Behavioral:sim_1:Functional:ArgSort_AXI_Test_Bench_X04_W1_F1} -tclbatch {ArgSort_AXI_Test_Bench_X04_W1_F1.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source ArgSort_AXI_Test_Bench_X04_W1_F1.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run all
        35 ns| MARCHAL < ArgSort_AXI_Test TEST 1 Start.
        55 ns| MARCHAL < ArgSort_AXI_Test TEST 1.1 Start.
      1565 ns| MARCHAL < ArgSort_AXI_Test TEST 1.1 Done.
      1585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.2 Start.
      3105 ns| MARCHAL < ArgSort_AXI_Test TEST 1.2 Done.
      3125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.3 Start.
      4665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.3 Done.
      4685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.4 Start.
      6245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.4 Done.
      6265 ns| MARCHAL < ArgSort_AXI_Test TEST 1.5 Start.
      8125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.5 Done.
      8145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.6 Start.
     10005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.6 Done.
     10025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.7 Start.
     11895 ns| MARCHAL < ArgSort_AXI_Test TEST 1.7 Done.
     11915 ns| MARCHAL < ArgSort_AXI_Test TEST 1.8 Start.
     13785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.8 Done.
     13805 ns| MARCHAL < ArgSort_AXI_Test TEST 1.9 Start.
     15685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.9 Done.
     15705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.10 Start.
     17585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.10 Done.
     17605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.11 Start.
     19495 ns| MARCHAL < ArgSort_AXI_Test TEST 1.11 Done.
     19515 ns| MARCHAL < ArgSort_AXI_Test TEST 1.12 Start.
     21405 ns| MARCHAL < ArgSort_AXI_Test TEST 1.12 Done.
     21425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.13 Start.
     23325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.13 Done.
     23345 ns| MARCHAL < ArgSort_AXI_Test TEST 1.14 Start.
     25245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.14 Done.
     25265 ns| MARCHAL < ArgSort_AXI_Test TEST 1.15 Start.
     27175 ns| MARCHAL < ArgSort_AXI_Test TEST 1.15 Done.
     27195 ns| MARCHAL < ArgSort_AXI_Test TEST 1.16 Start.
     29115 ns| MARCHAL < ArgSort_AXI_Test TEST 1.16 Done.
     29135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.17 Start.
     32225 ns| MARCHAL < ArgSort_AXI_Test TEST 1.17 Done.
     32245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.18 Start.
     35355 ns| MARCHAL < ArgSort_AXI_Test TEST 1.18 Done.
     35375 ns| MARCHAL < ArgSort_AXI_Test TEST 1.19 Start.
     38515 ns| MARCHAL < ArgSort_AXI_Test TEST 1.19 Done.
     38535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.20 Start.
     41705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.20 Done.
     41725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.21 Start.
     45195 ns| MARCHAL < ArgSort_AXI_Test TEST 1.21 Done.
     45215 ns| MARCHAL < ArgSort_AXI_Test TEST 1.22 Start.
     48705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.22 Done.
     48725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.23 Start.
     52245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.23 Done.
     52265 ns| MARCHAL < ArgSort_AXI_Test TEST 1.24 Start.
     55805 ns| MARCHAL < ArgSort_AXI_Test TEST 1.24 Done.
     55825 ns| MARCHAL < ArgSort_AXI_Test TEST 1.25 Start.
     59395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.25 Done.
     59415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.26 Start.
     63005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.26 Done.
     63025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.27 Start.
     66645 ns| MARCHAL < ArgSort_AXI_Test TEST 1.27 Done.
     66665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.28 Start.
     70305 ns| MARCHAL < ArgSort_AXI_Test TEST 1.28 Done.
     70325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.29 Start.
     73995 ns| MARCHAL < ArgSort_AXI_Test TEST 1.29 Done.
     74015 ns| MARCHAL < ArgSort_AXI_Test TEST 1.30 Start.
     77705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.30 Done.
     77725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.31 Start.
     81445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.31 Done.
     81465 ns| MARCHAL < ArgSort_AXI_Test TEST 1.32 Start.
     85215 ns| MARCHAL < ArgSort_AXI_Test TEST 1.32 Done.
     85235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.33 Start.
     89305 ns| MARCHAL < ArgSort_AXI_Test TEST 1.33 Done.
     89325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.34 Start.
     93405 ns| MARCHAL < ArgSort_AXI_Test TEST 1.34 Done.
     93425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.35 Start.
     97535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.35 Done.
     97555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.36 Start.
    101695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.36 Done.
    101715 ns| MARCHAL < ArgSort_AXI_Test TEST 1.37 Start.
    106155 ns| MARCHAL < ArgSort_AXI_Test TEST 1.37 Done.
    106175 ns| MARCHAL < ArgSort_AXI_Test TEST 1.38 Start.
    110635 ns| MARCHAL < ArgSort_AXI_Test TEST 1.38 Done.
    110655 ns| MARCHAL < ArgSort_AXI_Test TEST 1.39 Start.
    115145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.39 Done.
    115165 ns| MARCHAL < ArgSort_AXI_Test TEST 1.40 Start.
    119675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.40 Done.
    119695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.41 Start.
    124235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.41 Done.
    124255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.42 Start.
    128815 ns| MARCHAL < ArgSort_AXI_Test TEST 1.42 Done.
    128835 ns| MARCHAL < ArgSort_AXI_Test TEST 1.43 Start.
    133425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.43 Done.
    133445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.44 Start.
    138055 ns| MARCHAL < ArgSort_AXI_Test TEST 1.44 Done.
    138075 ns| MARCHAL < ArgSort_AXI_Test TEST 1.45 Start.
    142715 ns| MARCHAL < ArgSort_AXI_Test TEST 1.45 Done.
    142735 ns| MARCHAL < ArgSort_AXI_Test TEST 1.46 Start.
    147395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.46 Done.
    147415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.47 Start.
    152105 ns| MARCHAL < ArgSort_AXI_Test TEST 1.47 Done.
    152125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.48 Start.
    156845 ns| MARCHAL < ArgSort_AXI_Test TEST 1.48 Done.
    156865 ns| MARCHAL < ArgSort_AXI_Test TEST 1.49 Start.
    161905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.49 Done.
    161925 ns| MARCHAL < ArgSort_AXI_Test TEST 1.50 Start.
    166985 ns| MARCHAL < ArgSort_AXI_Test TEST 1.50 Done.
    167005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.51 Start.
    172095 ns| MARCHAL < ArgSort_AXI_Test TEST 1.51 Done.
    172115 ns| MARCHAL < ArgSort_AXI_Test TEST 1.52 Start.
    177235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.52 Done.
    177255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.53 Start.
    182675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.53 Done.
    182695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.54 Start.
    188135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.54 Done.
    188155 ns| MARCHAL < ArgSort_AXI_Test TEST 1.55 Start.
    193625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.55 Done.
    193645 ns| MARCHAL < ArgSort_AXI_Test TEST 1.56 Start.
    199135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.56 Done.
    199155 ns| MARCHAL < ArgSort_AXI_Test TEST 1.57 Start.
    204675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.57 Done.
    204695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.58 Start.
    210235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.58 Done.
    210255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.59 Start.
    215825 ns| MARCHAL < ArgSort_AXI_Test TEST 1.59 Done.
    215845 ns| MARCHAL < ArgSort_AXI_Test TEST 1.60 Start.
    221435 ns| MARCHAL < ArgSort_AXI_Test TEST 1.60 Done.
    221455 ns| MARCHAL < ArgSort_AXI_Test TEST 1.61 Start.
    227075 ns| MARCHAL < ArgSort_AXI_Test TEST 1.61 Done.
    227095 ns| MARCHAL < ArgSort_AXI_Test TEST 1.62 Start.
    232735 ns| MARCHAL < ArgSort_AXI_Test TEST 1.62 Done.
    232755 ns| MARCHAL < ArgSort_AXI_Test TEST 1.63 Start.
    238425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.63 Done.
    238445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.64 Start.
    244145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.64 Done.
    244165 ns| MARCHAL < ArgSort_AXI_Test TEST 1.65 Start.
    252535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.65 Done.
    252555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.66 Start.
    260965 ns| MARCHAL < ArgSort_AXI_Test TEST 1.66 Done.
    260985 ns| MARCHAL < ArgSort_AXI_Test TEST 1.67 Start.
    269445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.67 Done.
    269465 ns| MARCHAL < ArgSort_AXI_Test TEST 1.68 Start.
    277975 ns| MARCHAL < ArgSort_AXI_Test TEST 1.68 Done.
    277995 ns| MARCHAL < ArgSort_AXI_Test TEST 1.69 Start.
    286835 ns| MARCHAL < ArgSort_AXI_Test TEST 1.69 Done.
    286855 ns| MARCHAL < ArgSort_AXI_Test TEST 1.70 Start.
    295725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.70 Done.
    295745 ns| MARCHAL < ArgSort_AXI_Test TEST 1.71 Start.
    304665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.71 Done.
    304685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.72 Start.
    313645 ns| MARCHAL < ArgSort_AXI_Test TEST 1.72 Done.
    313665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.73 Start.
    322715 ns| MARCHAL < ArgSort_AXI_Test TEST 1.73 Done.
    322735 ns| MARCHAL < ArgSort_AXI_Test TEST 1.74 Start.
    331785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.74 Done.
    331805 ns| MARCHAL < ArgSort_AXI_Test TEST 1.75 Start.
    340905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.75 Done.
    340925 ns| MARCHAL < ArgSort_AXI_Test TEST 1.76 Start.
    350065 ns| MARCHAL < ArgSort_AXI_Test TEST 1.76 Done.
    350085 ns| MARCHAL < ArgSort_AXI_Test TEST 1.77 Start.
    359315 ns| MARCHAL < ArgSort_AXI_Test TEST 1.77 Done.
    359335 ns| MARCHAL < ArgSort_AXI_Test TEST 1.78 Start.
    368605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.78 Done.
    368625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.79 Start.
    377905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.79 Done.
    377925 ns| MARCHAL < ArgSort_AXI_Test TEST 1.80 Start.
    387255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.80 Done.
    387275 ns| MARCHAL < ArgSort_AXI_Test TEST 1.81 Start.
    396705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.81 Done.
    396725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.82 Start.
    406215 ns| MARCHAL < ArgSort_AXI_Test TEST 1.82 Done.
    406235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.83 Start.
    415765 ns| MARCHAL < ArgSort_AXI_Test TEST 1.83 Done.
    415785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.84 Start.
    425515 ns| MARCHAL < ArgSort_AXI_Test TEST 1.84 Done.
    425535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.85 Start.
    435545 ns| MARCHAL < ArgSort_AXI_Test TEST 1.85 Done.
    435565 ns| MARCHAL < ArgSort_AXI_Test TEST 1.86 Start.
    445525 ns| MARCHAL < ArgSort_AXI_Test TEST 1.86 Done.
    445545 ns| MARCHAL < ArgSort_AXI_Test TEST 1.87 Start.
    455585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.87 Done.
    455605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.88 Start.
    465755 ns| MARCHAL < ArgSort_AXI_Test TEST 1.88 Done.
    465775 ns| MARCHAL < ArgSort_AXI_Test TEST 1.89 Start.
    475885 ns| MARCHAL < ArgSort_AXI_Test TEST 1.89 Done.
    475905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.90 Start.
    486005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.90 Done.
    486025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.91 Start.
    496375 ns| MARCHAL < ArgSort_AXI_Test TEST 1.91 Done.
    496395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.92 Start.
    506665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.92 Done.
    506685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.93 Start.
    517005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.93 Done.
    517025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.94 Start.
    527395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.94 Done.
    527415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.95 Start.
    537865 ns| MARCHAL < ArgSort_AXI_Test TEST 1.95 Done.
    537885 ns| MARCHAL < ArgSort_AXI_Test TEST 1.96 Start.
    548385 ns| MARCHAL < ArgSort_AXI_Test TEST 1.96 Done.
    548405 ns| MARCHAL < ArgSort_AXI_Test TEST 1.97 Start.
    559045 ns| MARCHAL < ArgSort_AXI_Test TEST 1.97 Done.
    559065 ns| MARCHAL < ArgSort_AXI_Test TEST 1.98 Start.
    569755 ns| MARCHAL < ArgSort_AXI_Test TEST 1.98 Done.
    569775 ns| MARCHAL < ArgSort_AXI_Test TEST 1.99 Start.
    580535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.99 Done.
    580555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.100 Start.
    591465 ns| MARCHAL < ArgSort_AXI_Test TEST 1.100 Done.
    591485 ns| MARCHAL < ArgSort_AXI_Test TEST 1.101 Start.
    602605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.101 Done.
    602625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.102 Start.
    613895 ns| MARCHAL < ArgSort_AXI_Test TEST 1.102 Done.
    613915 ns| MARCHAL < ArgSort_AXI_Test TEST 1.103 Start.
    625295 ns| MARCHAL < ArgSort_AXI_Test TEST 1.103 Done.
    625315 ns| MARCHAL < ArgSort_AXI_Test TEST 1.104 Start.
    636615 ns| MARCHAL < ArgSort_AXI_Test TEST 1.104 Done.
    636635 ns| MARCHAL < ArgSort_AXI_Test TEST 1.105 Start.
    648115 ns| MARCHAL < ArgSort_AXI_Test TEST 1.105 Done.
    648135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.106 Start.
    659535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.106 Done.
    659555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.107 Start.
    671075 ns| MARCHAL < ArgSort_AXI_Test TEST 1.107 Done.
    671095 ns| MARCHAL < ArgSort_AXI_Test TEST 1.108 Start.
    682655 ns| MARCHAL < ArgSort_AXI_Test TEST 1.108 Done.
    682675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.109 Start.
    694305 ns| MARCHAL < ArgSort_AXI_Test TEST 1.109 Done.
    694325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.110 Start.
    705985 ns| MARCHAL < ArgSort_AXI_Test TEST 1.110 Done.
    706005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.111 Start.
    717745 ns| MARCHAL < ArgSort_AXI_Test TEST 1.111 Done.
    717765 ns| MARCHAL < ArgSort_AXI_Test TEST 1.112 Start.
    729585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.112 Done.
    729605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.113 Start.
    741575 ns| MARCHAL < ArgSort_AXI_Test TEST 1.113 Done.
    741595 ns| MARCHAL < ArgSort_AXI_Test TEST 1.114 Start.
    753585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.114 Done.
    753605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.115 Start.
    765675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.115 Done.
    765695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.116 Start.
    777835 ns| MARCHAL < ArgSort_AXI_Test TEST 1.116 Done.
    777855 ns| MARCHAL < ArgSort_AXI_Test TEST 1.117 Start.
    790435 ns| MARCHAL < ArgSort_AXI_Test TEST 1.117 Done.
    790455 ns| MARCHAL < ArgSort_AXI_Test TEST 1.118 Start.
    803125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.118 Done.
    803145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.119 Start.
    815705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.119 Done.
    815725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.120 Start.
    828395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.120 Done.
    828415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.121 Start.
    841065 ns| MARCHAL < ArgSort_AXI_Test TEST 1.121 Done.
    841085 ns| MARCHAL < ArgSort_AXI_Test TEST 1.122 Start.
    853765 ns| MARCHAL < ArgSort_AXI_Test TEST 1.122 Done.
    853785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.123 Start.
    866605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.123 Done.
    866625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.124 Start.
    879485 ns| MARCHAL < ArgSort_AXI_Test TEST 1.124 Done.
    879505 ns| MARCHAL < ArgSort_AXI_Test TEST 1.125 Start.
    892375 ns| MARCHAL < ArgSort_AXI_Test TEST 1.125 Done.
    892395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.126 Start.
    905345 ns| MARCHAL < ArgSort_AXI_Test TEST 1.126 Done.
    905365 ns| MARCHAL < ArgSort_AXI_Test TEST 1.127 Start.
    918325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.127 Done.
    918345 ns| MARCHAL < ArgSort_AXI_Test TEST 1.128 Start.
    931425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.128 Done.
    931445 ns| MARCHAL < ArgSort_AXI_Test TEST 1 Done.
  ***  
  ***  ERROR REPORT TEST_X04_W1_F1
  ***  
  ***  [ CSR ]
  ***    Error    : 0
  ***    Mismatch : 0
  ***    Warning  : 0
  ***  
  ***  [ STM AXI]
  ***    Error    : 0
  ***    Mismatch : 0
  ***    Warning  : 0
  ***  
  ***  [ MRG AXI]
  ***    Error    : 0
  ***    Mismatch : 0
  ***    Warning  : 0
  ***  
Failure: Simulation complete(success).
Time: 931466 ns  Iteration: 0  Process: /ArgSort_AXI_Test_Bench_X04_W1_F1/TB/line__848  File: /home/ichiro/tmp/Merge_Sorter/src/test/vhdl/argsort_axi_test_bench.vhd
$finish called at time : 931466 ns : File "/home/ichiro/tmp/Merge_Sorter/src/test/vhdl/argsort_axi_test_bench.vhd" Line 881
run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 10182.215 ; gain = 10.000 ; free physical = 27411 ; free virtual = 37279
xsim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 10182.215 ; gain = 88.992 ; free physical = 27411 ; free virtual = 37279
INFO: [USF-XSim-96] XSim completed. Design snapshot 'ArgSort_AXI_Test_Bench_X04_W1_F1_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for all
launch_simulation: Time (s): cpu = 00:02:37 ; elapsed = 00:02:24 . Memory (MB): peak = 10182.215 ; gain = 88.992 ; free physical = 27411 ; free virtual = 37279

Vivado で IP を作る

Requirement

• Xilinx Vivado 2025.1

shell$ cd Merge_Sorter/ip/argsort_axi/

Create add_sources.tcl

このディレクトリに次のような add_sources.yml というファイルがあります。

Merge_Sorter/ip/argsort_axi/add_sources.yml

- Library:
    Name     :  pipework
    Print    :  true
    Format   :  "add_vhdl_file sources_1 #{library_name} #{file_name}"
    PathList :  ["../../PipeWork/src/"]
    Use      :  ["SDPRAM(XILINX_ULTRASCALE_AUTO_SELECT)", "QUEUE_ARBITER(ONE_HOT_ARCH)"]

- Library:
    Name     :  Merge_Sorter
    Print    :  true
    Format   :  "add_vhdl_file sources_1 #{library_name} #{file_name}"
    PathList :  ["../../src/main/vhdl/"]
    Top      :  ["ArgSort_AXI"]

add_sources.yml にはライブラリごとに、Name(ライブラリの名前)、PathList(ファイルがあるパスのリスト)、Format(出力するさいのフォーマット)が記述されています。また、Top には階層構造のトップになる entity 名のリストが記載されています。

この add_sources.yml を次のように ruby スクリプトに食わせると add_sources.tcl というファイルが出来ます。

shell$ ../../PipeWork/tools/vhdl-archiver.rb -v --config add_sources.yml > add_sources.tcl

add_sources.tcl（ちょっと長いので折り畳み)

Merge_Sorter/sim/vivado/argsort_axi/add_sources.tcl

add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/components.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/float_intake_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/float_outlet_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/pipeline_register_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_types.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/count_down_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/count_up_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/delay_adjuster.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/delay_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/float_intake_manifold_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/float_outlet_manifold_valve.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/justifier.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/pipeline_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/queue_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/reducer.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/syncronizer.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/syncronizer_input_pending_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_components.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_control_register.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_components.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_data_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/chopper.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/pool_intake_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/pool_outlet_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_controller_intake_side.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_controller_outlet_side.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_flow_syncronizer.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_data_outlet_port.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_master_address_channel_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_master_transfer_queue.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/queue_arbiter.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/queue_receiver.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/sdpram.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_stream_intake_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/pump/pump_stream_outlet_controller.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_master_read_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_master_write_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/queue_tree_arbiter.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_register_read_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_register_write_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/register_access_decoder.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/register_access_syncronizer.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/axi4/axi4_register_interface.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/register_access_adapter.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/queue_arbiter_one_hot_arch.vhd
add_vhdl_file sources_1 PIPEWORK ../../PipeWork/src/components/sdpram_xilinx_ultrascale_auto_select.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/sorting_network.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/core_components.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word_compare.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word_pipeline_register.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/oddeven_mergesort_network.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/sorting_network_core.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word_queue.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/interface.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/merge_sorter_node.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word_fifo.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word_reducer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/interface_components.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/merge_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/merge_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/core_intake_fifo.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/core_stream_intake.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/merge_sorter_tree.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/word_drop_none.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/interface_controller.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/merge_axi_reader.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/interface/merge_axi_writer.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/core/merge_sorter_core.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd
add_vhdl_file sources_1 MERGE_SORTER ../../src/main/vhdl/examples/argsort_axi/argsort_axi.vhd

Create IP

この add_source.tcl を create_ip.tcl を使って Vivado のプロジェクトを作る際に、読み込ませます。

Merge_Sorter/ip/argsort_axi/create_ip.tcl

  :
proc add_vhdl_file {fileset library_name file_name} {
    set file    [file normalize $file_name]
    set fileset [get_filesets   $fileset  ] 
    add_files -norecurse -fileset $fileset $file
    set file_obj [get_files -of_objects $fileset $file]
    set_property "file_type" "VHDL"        $file_obj
    set_property "library"   $library_name $file_obj
}
source "add_files.tcl"
  :

Vivado > Tools > Run Tcl scripts... > Merge_Sorter/ip/argsort_axi/create_ip.tcl

nvc でシミュレーション

nvc は次の URL で公開されている LLVM ベースの VHDL シミューレーターです。

• https://github.com/nickg/nvc

Requirement

• nvc 1.18 以降

shell$ cd Merge_Sorter/sim/nvc/argsort_axi/

Create analyze_libs.sh

このディレクトリに次のような libs.yml というファイルがあります。

Merge_Sorter/sim/nvc/argsort_axi/libs.yml

- Library:
    Name     :  DUMMY_PLUG
    Print    :  true
    Format   :  "nvc -L ./ --work=#{library_name} -a --relaxed #{file_name}"
    Exclude  :  ["../../../Dummy_Plug/src/main/vhdl/core/sync_alt.vhd"]
    PathList :  ["../../../Dummy_Plug/src/main/vhdl/"]

- Library:
    Name     :  PIPEWORK
    Print    :  true
    Format   :  "nvc -L ./ --work=#{library_name} -a #{file_name}"
    Exclude  :  ["../../../PipeWork/src/components/sdpram_altera_auto_select.vhd",
                 "../../../PipeWork/src/components/sdpram_xilinx_auto_select.vhd",
                 "../../../PipeWork/src/components/sdpram_xilinx_ultrascale_auto_select.vhd"]
    PathList :  ["../../../PipeWork/src/"]

- Library:
    Name     :  MERGE_SORTER
    Print    :  true
    Format   :  "nvc -L ./ --work=#{library_name} -a #{file_name}"
    PathList :  ["../../../src/main/vhdl"]

- Library:
    Name     :  WORK
    Print    :  true
    Format   :  "nvc -L ./ --work=#{library_name} -a #{file_name}"
    PathList :  ["../../../src/test/vhdl"]
    Top      :  ["ArgSort_AXI_Test_Bench"]

この libs.yml を次のように ruby スクリプトに食わせると analyze_libs.sh というファイルが出来ます。

shell$ ../../../PipeWork/tools/vhdl-archiver.rb -v --config libs.yml > analyze_libs.sh

analyze_libs.sh（ちょっと長いので折り畳み)

Merge_Sorter/sim/nvc/argsort_axi/analyze_libs.sh

nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/core/util.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/core/reader.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/core/sync.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/core/vocal.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_types.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/core/core.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_core.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_channel_player.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_master_player.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/axi4/axi4_models.vhd
nvc -L ./ --work=DUMMY_PLUG -a --relaxed ../../../Dummy_Plug/src/main/vhdl/core/marchal.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/components.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/float_intake_valve.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/float_outlet_valve.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/pipeline_register_controller.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_types.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/count_down_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/count_up_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/delay_adjuster.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/delay_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/float_intake_manifold_valve.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/float_outlet_manifold_valve.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/justifier.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/pipeline_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/queue_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/reducer.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/syncronizer.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/syncronizer_input_pending_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_components.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_control_register.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_components.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_data_port.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/chopper.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/pool_intake_port.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/pool_outlet_port.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_controller_intake_side.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_controller_outlet_side.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_flow_syncronizer.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_data_outlet_port.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_master_address_channel_controller.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_master_transfer_queue.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/queue_arbiter.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/queue_receiver.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/sdpram.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_stream_intake_controller.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/pump/pump_stream_outlet_controller.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_master_read_interface.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_master_write_interface.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/queue_tree_arbiter.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_register_read_interface.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_register_write_interface.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/register_access_decoder.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/register_access_syncronizer.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/axi4/axi4_register_interface.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/register_access_adapter.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/queue_arbiter_integer_arch.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/queue_arbiter_one_hot_arch.vhd
nvc -L ./ --work=PIPEWORK -a ../../../PipeWork/src/components/sdpram_model.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/sorting_network.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/core_components.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word_compare.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word_pipeline_register.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/oddeven_mergesort_network.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/sorting_network_core.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word_queue.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/interface.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/merge_sorter_node.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word_fifo.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word_reducer.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_components.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_reader.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_writer.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/interface_components.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/merge_reader.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/merge_writer.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/core_intake_fifo.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/core_stream_intake.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/merge_sorter_tree.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/word_drop_none.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_reader.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_writer.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/interface_controller.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/merge_axi_reader.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/interface/merge_axi_writer.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/core/merge_sorter_core.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_axi_interface.vhd
nvc -L ./ --work=MERGE_SORTER -a ../../../src/main/vhdl/examples/argsort_axi/argsort_axi.vhd
nvc -L ./ --work=WORK -a ../../../src/test/vhdl/argsort_axi_test_bench.vhd

Run Simulation

shell$ make test_x04_w1_f1
sh analyze_libs.sh
** Warning: shared variable MEM must have protected type
     > /home/ichiro/tmp/Merge_Sorter/Dummy_Plug/src/main/vhdl/axi4/axi4_memory_player.vhd:231
     |
 231 |     shared variable  mem        :  MEMORY_TYPE;
     |                      ^^^
nvc -L ./ -M 32M --work=WORK -e  ArgSort_AXI_Test_Bench_x04_w1_f1
cat ../../../src/test/scenarios/argsort_axi/test_1.snr ../../../src/test/scenarios/argsort_axi/test_2.snr ../../../src/test/scenarios/argsort_axi/test_3.snr >  test_x04_w1_f1.snr
nvc -L ./ -M 32M --work=WORK -r  ArgSort_AXI_Test_Bench_x04_w1_f1
        35 ns| MARCHAL < ArgSort_AXI_Test TEST 1 Start.
        55 ns| MARCHAL < ArgSort_AXI_Test TEST 1.1 Start.
      1565 ns| MARCHAL < ArgSort_AXI_Test TEST 1.1 Done.
      1585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.2 Start.
      3105 ns| MARCHAL < ArgSort_AXI_Test TEST 1.2 Done.
      3125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.3 Start.
      4665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.3 Done.
      4685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.4 Start.
      6245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.4 Done.
      6265 ns| MARCHAL < ArgSort_AXI_Test TEST 1.5 Start.
      8125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.5 Done.
      8145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.6 Start.
     10005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.6 Done.
     10025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.7 Start.
     11895 ns| MARCHAL < ArgSort_AXI_Test TEST 1.7 Done.
     11915 ns| MARCHAL < ArgSort_AXI_Test TEST 1.8 Start.
     13785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.8 Done.
     13805 ns| MARCHAL < ArgSort_AXI_Test TEST 1.9 Start.
     15685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.9 Done.
     15705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.10 Start.
     17585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.10 Done.
     17605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.11 Start.
     19495 ns| MARCHAL < ArgSort_AXI_Test TEST 1.11 Done.
     19515 ns| MARCHAL < ArgSort_AXI_Test TEST 1.12 Start.
     21405 ns| MARCHAL < ArgSort_AXI_Test TEST 1.12 Done.
     21425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.13 Start.
     23325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.13 Done.
     23345 ns| MARCHAL < ArgSort_AXI_Test TEST 1.14 Start.
     25245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.14 Done.
     25265 ns| MARCHAL < ArgSort_AXI_Test TEST 1.15 Start.
     27175 ns| MARCHAL < ArgSort_AXI_Test TEST 1.15 Done.
     27195 ns| MARCHAL < ArgSort_AXI_Test TEST 1.16 Start.
     29115 ns| MARCHAL < ArgSort_AXI_Test TEST 1.16 Done.
     29135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.17 Start.
     32225 ns| MARCHAL < ArgSort_AXI_Test TEST 1.17 Done.
     32245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.18 Start.
     35355 ns| MARCHAL < ArgSort_AXI_Test TEST 1.18 Done.
     35375 ns| MARCHAL < ArgSort_AXI_Test TEST 1.19 Start.
     38515 ns| MARCHAL < ArgSort_AXI_Test TEST 1.19 Done.
     38535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.20 Start.
     41705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.20 Done.
     41725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.21 Start.
     45195 ns| MARCHAL < ArgSort_AXI_Test TEST 1.21 Done.
     45215 ns| MARCHAL < ArgSort_AXI_Test TEST 1.22 Start.
     48705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.22 Done.
     48725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.23 Start.
     52245 ns| MARCHAL < ArgSort_AXI_Test TEST 1.23 Done.
     52265 ns| MARCHAL < ArgSort_AXI_Test TEST 1.24 Start.
     55805 ns| MARCHAL < ArgSort_AXI_Test TEST 1.24 Done.
     55825 ns| MARCHAL < ArgSort_AXI_Test TEST 1.25 Start.
     59395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.25 Done.
     59415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.26 Start.
     63005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.26 Done.
     63025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.27 Start.
     66645 ns| MARCHAL < ArgSort_AXI_Test TEST 1.27 Done.
     66665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.28 Start.
     70305 ns| MARCHAL < ArgSort_AXI_Test TEST 1.28 Done.
     70325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.29 Start.
     73995 ns| MARCHAL < ArgSort_AXI_Test TEST 1.29 Done.
     74015 ns| MARCHAL < ArgSort_AXI_Test TEST 1.30 Start.
     77705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.30 Done.
     77725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.31 Start.
     81445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.31 Done.
     81465 ns| MARCHAL < ArgSort_AXI_Test TEST 1.32 Start.
     85215 ns| MARCHAL < ArgSort_AXI_Test TEST 1.32 Done.
     85235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.33 Start.
     89305 ns| MARCHAL < ArgSort_AXI_Test TEST 1.33 Done.
     89325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.34 Start.
     93405 ns| MARCHAL < ArgSort_AXI_Test TEST 1.34 Done.
     93425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.35 Start.
     97535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.35 Done.
     97555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.36 Start.
    101695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.36 Done.
    101715 ns| MARCHAL < ArgSort_AXI_Test TEST 1.37 Start.
    106155 ns| MARCHAL < ArgSort_AXI_Test TEST 1.37 Done.
    106175 ns| MARCHAL < ArgSort_AXI_Test TEST 1.38 Start.
    110635 ns| MARCHAL < ArgSort_AXI_Test TEST 1.38 Done.
    110655 ns| MARCHAL < ArgSort_AXI_Test TEST 1.39 Start.
    115145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.39 Done.
    115165 ns| MARCHAL < ArgSort_AXI_Test TEST 1.40 Start.
    119675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.40 Done.
    119695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.41 Start.
    124235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.41 Done.
    124255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.42 Start.
    128815 ns| MARCHAL < ArgSort_AXI_Test TEST 1.42 Done.
    128835 ns| MARCHAL < ArgSort_AXI_Test TEST 1.43 Start.
    133425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.43 Done.
    133445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.44 Start.
    138055 ns| MARCHAL < ArgSort_AXI_Test TEST 1.44 Done.
    138075 ns| MARCHAL < ArgSort_AXI_Test TEST 1.45 Start.
    142715 ns| MARCHAL < ArgSort_AXI_Test TEST 1.45 Done.
    142735 ns| MARCHAL < ArgSort_AXI_Test TEST 1.46 Start.
    147395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.46 Done.
    147415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.47 Start.
    152105 ns| MARCHAL < ArgSort_AXI_Test TEST 1.47 Done.
    152125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.48 Start.
    156845 ns| MARCHAL < ArgSort_AXI_Test TEST 1.48 Done.
    156865 ns| MARCHAL < ArgSort_AXI_Test TEST 1.49 Start.
    161905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.49 Done.
    161925 ns| MARCHAL < ArgSort_AXI_Test TEST 1.50 Start.
    166985 ns| MARCHAL < ArgSort_AXI_Test TEST 1.50 Done.
    167005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.51 Start.
    172095 ns| MARCHAL < ArgSort_AXI_Test TEST 1.51 Done.
    172115 ns| MARCHAL < ArgSort_AXI_Test TEST 1.52 Start.
    177235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.52 Done.
    177255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.53 Start.
    182675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.53 Done.
    182695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.54 Start.
    188135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.54 Done.
    188155 ns| MARCHAL < ArgSort_AXI_Test TEST 1.55 Start.
    193625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.55 Done.
    193645 ns| MARCHAL < ArgSort_AXI_Test TEST 1.56 Start.
    199135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.56 Done.
    199155 ns| MARCHAL < ArgSort_AXI_Test TEST 1.57 Start.
    204675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.57 Done.
    204695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.58 Start.
    210235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.58 Done.
    210255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.59 Start.
    215825 ns| MARCHAL < ArgSort_AXI_Test TEST 1.59 Done.
    215845 ns| MARCHAL < ArgSort_AXI_Test TEST 1.60 Start.
    221435 ns| MARCHAL < ArgSort_AXI_Test TEST 1.60 Done.
    221455 ns| MARCHAL < ArgSort_AXI_Test TEST 1.61 Start.
    227075 ns| MARCHAL < ArgSort_AXI_Test TEST 1.61 Done.
    227095 ns| MARCHAL < ArgSort_AXI_Test TEST 1.62 Start.
    232735 ns| MARCHAL < ArgSort_AXI_Test TEST 1.62 Done.
    232755 ns| MARCHAL < ArgSort_AXI_Test TEST 1.63 Start.
    238425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.63 Done.
    238445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.64 Start.
    244145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.64 Done.
    244165 ns| MARCHAL < ArgSort_AXI_Test TEST 1.65 Start.
    252535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.65 Done.
    252555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.66 Start.
    260965 ns| MARCHAL < ArgSort_AXI_Test TEST 1.66 Done.
    260985 ns| MARCHAL < ArgSort_AXI_Test TEST 1.67 Start.
    269445 ns| MARCHAL < ArgSort_AXI_Test TEST 1.67 Done.
    269465 ns| MARCHAL < ArgSort_AXI_Test TEST 1.68 Start.
    277975 ns| MARCHAL < ArgSort_AXI_Test TEST 1.68 Done.
    277995 ns| MARCHAL < ArgSort_AXI_Test TEST 1.69 Start.
    286835 ns| MARCHAL < ArgSort_AXI_Test TEST 1.69 Done.
    286855 ns| MARCHAL < ArgSort_AXI_Test TEST 1.70 Start.
    295725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.70 Done.
    295745 ns| MARCHAL < ArgSort_AXI_Test TEST 1.71 Start.
    304665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.71 Done.
    304685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.72 Start.
    313645 ns| MARCHAL < ArgSort_AXI_Test TEST 1.72 Done.
    313665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.73 Start.
    322715 ns| MARCHAL < ArgSort_AXI_Test TEST 1.73 Done.
    322735 ns| MARCHAL < ArgSort_AXI_Test TEST 1.74 Start.
    331785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.74 Done.
    331805 ns| MARCHAL < ArgSort_AXI_Test TEST 1.75 Start.
    340905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.75 Done.
    340925 ns| MARCHAL < ArgSort_AXI_Test TEST 1.76 Start.
    350065 ns| MARCHAL < ArgSort_AXI_Test TEST 1.76 Done.
    350085 ns| MARCHAL < ArgSort_AXI_Test TEST 1.77 Start.
    359315 ns| MARCHAL < ArgSort_AXI_Test TEST 1.77 Done.
    359335 ns| MARCHAL < ArgSort_AXI_Test TEST 1.78 Start.
    368605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.78 Done.
    368625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.79 Start.
    377905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.79 Done.
    377925 ns| MARCHAL < ArgSort_AXI_Test TEST 1.80 Start.
    387255 ns| MARCHAL < ArgSort_AXI_Test TEST 1.80 Done.
    387275 ns| MARCHAL < ArgSort_AXI_Test TEST 1.81 Start.
    396705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.81 Done.
    396725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.82 Start.
    406215 ns| MARCHAL < ArgSort_AXI_Test TEST 1.82 Done.
    406235 ns| MARCHAL < ArgSort_AXI_Test TEST 1.83 Start.
    415765 ns| MARCHAL < ArgSort_AXI_Test TEST 1.83 Done.
    415785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.84 Start.
    425515 ns| MARCHAL < ArgSort_AXI_Test TEST 1.84 Done.
    425535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.85 Start.
    435545 ns| MARCHAL < ArgSort_AXI_Test TEST 1.85 Done.
    435565 ns| MARCHAL < ArgSort_AXI_Test TEST 1.86 Start.
    445525 ns| MARCHAL < ArgSort_AXI_Test TEST 1.86 Done.
    445545 ns| MARCHAL < ArgSort_AXI_Test TEST 1.87 Start.
    455585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.87 Done.
    455605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.88 Start.
    465755 ns| MARCHAL < ArgSort_AXI_Test TEST 1.88 Done.
    465775 ns| MARCHAL < ArgSort_AXI_Test TEST 1.89 Start.
    475885 ns| MARCHAL < ArgSort_AXI_Test TEST 1.89 Done.
    475905 ns| MARCHAL < ArgSort_AXI_Test TEST 1.90 Start.
    486005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.90 Done.
    486025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.91 Start.
    496375 ns| MARCHAL < ArgSort_AXI_Test TEST 1.91 Done.
    496395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.92 Start.
    506665 ns| MARCHAL < ArgSort_AXI_Test TEST 1.92 Done.
    506685 ns| MARCHAL < ArgSort_AXI_Test TEST 1.93 Start.
    517005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.93 Done.
    517025 ns| MARCHAL < ArgSort_AXI_Test TEST 1.94 Start.
    527395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.94 Done.
    527415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.95 Start.
    537865 ns| MARCHAL < ArgSort_AXI_Test TEST 1.95 Done.
    537885 ns| MARCHAL < ArgSort_AXI_Test TEST 1.96 Start.
    548385 ns| MARCHAL < ArgSort_AXI_Test TEST 1.96 Done.
    548405 ns| MARCHAL < ArgSort_AXI_Test TEST 1.97 Start.
    559045 ns| MARCHAL < ArgSort_AXI_Test TEST 1.97 Done.
    559065 ns| MARCHAL < ArgSort_AXI_Test TEST 1.98 Start.
    569755 ns| MARCHAL < ArgSort_AXI_Test TEST 1.98 Done.
    569775 ns| MARCHAL < ArgSort_AXI_Test TEST 1.99 Start.
    580535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.99 Done.
    580555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.100 Start.
    591465 ns| MARCHAL < ArgSort_AXI_Test TEST 1.100 Done.
    591485 ns| MARCHAL < ArgSort_AXI_Test TEST 1.101 Start.
    602605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.101 Done.
    602625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.102 Start.
    613895 ns| MARCHAL < ArgSort_AXI_Test TEST 1.102 Done.
    613915 ns| MARCHAL < ArgSort_AXI_Test TEST 1.103 Start.
    625295 ns| MARCHAL < ArgSort_AXI_Test TEST 1.103 Done.
    625315 ns| MARCHAL < ArgSort_AXI_Test TEST 1.104 Start.
    636615 ns| MARCHAL < ArgSort_AXI_Test TEST 1.104 Done.
    636635 ns| MARCHAL < ArgSort_AXI_Test TEST 1.105 Start.
    648115 ns| MARCHAL < ArgSort_AXI_Test TEST 1.105 Done.
    648135 ns| MARCHAL < ArgSort_AXI_Test TEST 1.106 Start.
    659535 ns| MARCHAL < ArgSort_AXI_Test TEST 1.106 Done.
    659555 ns| MARCHAL < ArgSort_AXI_Test TEST 1.107 Start.
    671075 ns| MARCHAL < ArgSort_AXI_Test TEST 1.107 Done.
    671095 ns| MARCHAL < ArgSort_AXI_Test TEST 1.108 Start.
    682655 ns| MARCHAL < ArgSort_AXI_Test TEST 1.108 Done.
    682675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.109 Start.
    694305 ns| MARCHAL < ArgSort_AXI_Test TEST 1.109 Done.
    694325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.110 Start.
    705985 ns| MARCHAL < ArgSort_AXI_Test TEST 1.110 Done.
    706005 ns| MARCHAL < ArgSort_AXI_Test TEST 1.111 Start.
    717745 ns| MARCHAL < ArgSort_AXI_Test TEST 1.111 Done.
    717765 ns| MARCHAL < ArgSort_AXI_Test TEST 1.112 Start.
    729585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.112 Done.
    729605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.113 Start.
    741575 ns| MARCHAL < ArgSort_AXI_Test TEST 1.113 Done.
    741595 ns| MARCHAL < ArgSort_AXI_Test TEST 1.114 Start.
    753585 ns| MARCHAL < ArgSort_AXI_Test TEST 1.114 Done.
    753605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.115 Start.
    765675 ns| MARCHAL < ArgSort_AXI_Test TEST 1.115 Done.
    765695 ns| MARCHAL < ArgSort_AXI_Test TEST 1.116 Start.
    777835 ns| MARCHAL < ArgSort_AXI_Test TEST 1.116 Done.
    777855 ns| MARCHAL < ArgSort_AXI_Test TEST 1.117 Start.
    790435 ns| MARCHAL < ArgSort_AXI_Test TEST 1.117 Done.
    790455 ns| MARCHAL < ArgSort_AXI_Test TEST 1.118 Start.
    803125 ns| MARCHAL < ArgSort_AXI_Test TEST 1.118 Done.
    803145 ns| MARCHAL < ArgSort_AXI_Test TEST 1.119 Start.
    815705 ns| MARCHAL < ArgSort_AXI_Test TEST 1.119 Done.
    815725 ns| MARCHAL < ArgSort_AXI_Test TEST 1.120 Start.
    828395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.120 Done.
    828415 ns| MARCHAL < ArgSort_AXI_Test TEST 1.121 Start.
    841065 ns| MARCHAL < ArgSort_AXI_Test TEST 1.121 Done.
    841085 ns| MARCHAL < ArgSort_AXI_Test TEST 1.122 Start.
    853765 ns| MARCHAL < ArgSort_AXI_Test TEST 1.122 Done.
    853785 ns| MARCHAL < ArgSort_AXI_Test TEST 1.123 Start.
    866605 ns| MARCHAL < ArgSort_AXI_Test TEST 1.123 Done.
    866625 ns| MARCHAL < ArgSort_AXI_Test TEST 1.124 Start.
    879485 ns| MARCHAL < ArgSort_AXI_Test TEST 1.124 Done.
    879505 ns| MARCHAL < ArgSort_AXI_Test TEST 1.125 Start.
    892375 ns| MARCHAL < ArgSort_AXI_Test TEST 1.125 Done.
    892395 ns| MARCHAL < ArgSort_AXI_Test TEST 1.126 Start.
    905345 ns| MARCHAL < ArgSort_AXI_Test TEST 1.126 Done.
    905365 ns| MARCHAL < ArgSort_AXI_Test TEST 1.127 Start.
    918325 ns| MARCHAL < ArgSort_AXI_Test TEST 1.127 Done.
    918345 ns| MARCHAL < ArgSort_AXI_Test TEST 1.128 Start.
    931425 ns| MARCHAL < ArgSort_AXI_Test TEST 1.128 Done.
    931445 ns| MARCHAL < ArgSort_AXI_Test TEST 1 Done.
    931485 ns| MARCHAL < ArgSort_AXI_Test TEST 2 Start.
    931505 ns| MARCHAL < ArgSort_AXI_Test TEST 2.1 SIZE=512 Start.
    982705 ns| MARCHAL < ArgSort_AXI_Test TEST 2.1 SIZE=512 Done.
    982725 ns| MARCHAL < ArgSort_AXI_Test TEST 2.2 SIZE=768 Start.
   1052835 ns| MARCHAL < ArgSort_AXI_Test TEST 2.2 SIZE=768 Done.
   1052855 ns| MARCHAL < ArgSort_AXI_Test TEST 2.3 SIZE=1024 Start.
   1144325 ns| MARCHAL < ArgSort_AXI_Test TEST 2.3 SIZE=1024 Done.
   1144345 ns| MARCHAL < ArgSort_AXI_Test TEST 2 Done.
   1144385 ns| MARCHAL < ArgSort_AXI_Test TEST 3 Start.
   1144405 ns| MARCHAL < ArgSort_AXI_Test TEST 3.1 SIZE=223 Start.
   1165955 ns| MARCHAL < ArgSort_AXI_Test TEST 3.1 SIZE=223 Done.
   1165975 ns| MARCHAL < ArgSort_AXI_Test TEST 3.2 SIZE=278 Start.
   1199605 ns| MARCHAL < ArgSort_AXI_Test TEST 3.2 SIZE=278 Done.
   1199625 ns| MARCHAL < ArgSort_AXI_Test TEST 3.3 SIZE=993 Start.
   1287545 ns| MARCHAL < ArgSort_AXI_Test TEST 3.3 SIZE=993 Done.
   1287565 ns| MARCHAL < ArgSort_AXI_Test TEST 3.4 SIZE=409 Start.
   1328175 ns| MARCHAL < ArgSort_AXI_Test TEST 3.4 SIZE=409 Done.
   1328195 ns| MARCHAL < ArgSort_AXI_Test TEST 3.5 SIZE=654 Start.
   1387865 ns| MARCHAL < ArgSort_AXI_Test TEST 3.5 SIZE=654 Done.
   1387885 ns| MARCHAL < ArgSort_AXI_Test TEST 3.6 SIZE=637 Start.
   1446185 ns| MARCHAL < ArgSort_AXI_Test TEST 3.6 SIZE=637 Done.
   1446205 ns| MARCHAL < ArgSort_AXI_Test TEST 3.7 SIZE=891 Start.
   1524555 ns| MARCHAL < ArgSort_AXI_Test TEST 3.7 SIZE=891 Done.
   1524575 ns| MARCHAL < ArgSort_AXI_Test TEST 3.8 SIZE=941 Start.
   1607325 ns| MARCHAL < ArgSort_AXI_Test TEST 3.8 SIZE=941 Done.
   1607345 ns| MARCHAL < ArgSort_AXI_Test TEST 3.9 SIZE=806 Start.
   1681795 ns| MARCHAL < ArgSort_AXI_Test TEST 3.9 SIZE=806 Done.
   1681815 ns| MARCHAL < ArgSort_AXI_Test TEST 3.10 SIZE=71 Start.
   1690735 ns| MARCHAL < ArgSort_AXI_Test TEST 3.10 SIZE=71 Done.
   1690755 ns| MARCHAL < ArgSort_AXI_Test TEST 3.11 SIZE=501 Start.
   1740895 ns| MARCHAL < ArgSort_AXI_Test TEST 3.11 SIZE=501 Done.
   1740915 ns| MARCHAL < ArgSort_AXI_Test TEST 3.12 SIZE=572 Start.
   1796965 ns| MARCHAL < ArgSort_AXI_Test TEST 3.12 SIZE=572 Done.
   1796985 ns| MARCHAL < ArgSort_AXI_Test TEST 3.13 SIZE=360 Start.
   1834215 ns| MARCHAL < ArgSort_AXI_Test TEST 3.13 SIZE=360 Done.
   1834235 ns| MARCHAL < ArgSort_AXI_Test TEST 3.14 SIZE=96 Start.
   1844715 ns| MARCHAL < ArgSort_AXI_Test TEST 3.14 SIZE=96 Done.
   1844735 ns| MARCHAL < ArgSort_AXI_Test TEST 3.15 SIZE=810 Start.
   1919485 ns| MARCHAL < ArgSort_AXI_Test TEST 3.15 SIZE=810 Done.
   1919505 ns| MARCHAL < ArgSort_AXI_Test TEST 3.16 SIZE=525 Start.
   1973975 ns| MARCHAL < ArgSort_AXI_Test TEST 3.16 SIZE=525 Done.
   1973995 ns| MARCHAL < ArgSort_AXI_Test TEST 3.17 SIZE=392 Start.
   2013105 ns| MARCHAL < ArgSort_AXI_Test TEST 3.17 SIZE=392 Done.
   2013125 ns| MARCHAL < ArgSort_AXI_Test TEST 3.18 SIZE=360 Start.
   2050345 ns| MARCHAL < ArgSort_AXI_Test TEST 3.18 SIZE=360 Done.
   2050365 ns| MARCHAL < ArgSort_AXI_Test TEST 3.19 SIZE=729 Start.
   2116975 ns| MARCHAL < ArgSort_AXI_Test TEST 3.19 SIZE=729 Done.
   2116995 ns| MARCHAL < ArgSort_AXI_Test TEST 3.20 SIZE=43 Start.
   2121595 ns| MARCHAL < ArgSort_AXI_Test TEST 3.20 SIZE=43 Done.
   2121615 ns| MARCHAL < ArgSort_AXI_Test TEST 3 Done.
  ***  
  ***  ERROR REPORT TEST_X04_W1_F1
  ***  
  ***  [ CSR ]
  ***    Error    : 0
  ***    Mismatch : 0
  ***    Warning  : 0
  ***  
  ***  [ STM AXI]
  ***    Error    : 0
  ***    Mismatch : 0
  ***    Warning  : 0
  ***  
  ***  [ MRG AXI]
  ***    Error    : 0
  ***    Mismatch : 0
  ***    Warning  : 0
  ***  
** Note: 2121636ns+0: Simulation complete(success).
   Process :argsort_axi_test_bench_x04_w1_f1:tb:_p8 at /home/ichiro/tmp/Merge_Sorter/src/test/vhdl/argsort_axi_test_bench.vhd:848

参考

• https://github.com/ikwzm/PipeWork/blob/master/tools/vhdl-archiver.rb
• https://github.com/ikwzm/PipeWork/blob/master/tools/lib/pipework/vhdl-reader.rb
• 『VHDL で書くマージソーター(ArgSort IP)』@Qiita
• 『VHDLで作る AXI Bus Function Model 「Dummy_Plug」 の紹介』@Qiita
• 『VHDLで下位ブロックを呼び出す2つの方法』@Qiita
• 『VHDLのentity宣言をcomponent宣言に変換してpackageファイルを作るrubyスクリプト』@Qiita
• 『VivadoをGUIを使わずに実行するためのTclスクリプト達』@Qiita
• https://github.com/ikwzm/Merge_Sorter
• https://github.com/nickg/nvc