SystemVerilogのエラー修正
解決したいこと
SystemVerilog の学習中で，エラーを修正したいです．
発生している問題・エラー
ksa.sv:12: error: Net data type requires SystemVerilog.
ksa.sv:12: error: Net data type requires SystemVerilog.
ksa.sv:13: error: Net data type requires SystemVerilog.
ksa.sv:14: error: Net data type requires SystemVerilog.
ksa.sv:15: error: Net data type requires SystemVerilog.
ksa.sv:24: syntax error
ksa.sv:24: error: Invalid module instantiation
ksa.sv:33: syntax error
ksa.sv:33: error: Syntax error in continuous assignment
ksa.sv:34: syntax error
ksa.sv:34: error: Syntax error in continuous assignment
ksa.sv:35: syntax error
ksa.sv:35: error: Syntax error in continuous assignment
ksa.sv:36: syntax error
ksa.sv:36: error: Syntax error in continuous assignment
ksa.sv:39: syntax error
ksa.sv:39: error: Invalid module instantiation
ksa.sv:40: error: Invalid module instantiation
ksa.sv:44: syntax error
ksa.sv:44: error: Invalid module instantiation
ksa.sv:45: error: Invalid module instantiation
ksa.sv:50: syntax error
ksa.sv:50: error: Invalid module instantiation
ksa.sv:53: syntax error
ksa.sv:53: error: Invalid module instantiation
ksa.sv:54: syntax error
ksa.sv:54: error: Invalid module item.
ksa.sv:56: syntax error
ksa.sv:57: error: Invalid module item.
ksa.sv:60: syntax error
ksa.sv:60: error: Invalid module instantiation
該当するソースコード
`define Ready 4'd0
`define Get_Address_s_i 4'd1
`define Get_s_i 4'd2
`define Calculate_j 4'd3
`define Get_Address_s_j 4'd4
`define Get_s_j 4'd5
`define Write_s_i 4'd6
`define Write_s_j 4'd7
`define Calculate_i 4'd8
`define Done 4'd9
module ksa(input logic clk, input logic rst_n,
input logic en, output logic rdy,
input logic [23:0] key,
output logic [7:0] addr, input logic [7:0] rddata, output logic [7:0] wrdata, output logic wren);
// your code here
logic start_counter, increment, new_j;
logic read_i, read_j, swap_i, swap_j;
logic [7:0] i,j;
logic [7:0] s_i, key_i, s_j;
logic [4:0] state = Ready;
always_ff @(posedge clk, negedge rst_n)
begin
if (!rst_n)
state = `Ready;
case(state)
`Ready:
begin
i <= 8'b0;
j <= 8'b0;
s_i <= 8'b0;
s_j <= 8'b0;
if (en)
begin
state <= `Get_Address_s_i;
rdy <= 1'b0;
end
else
begin
state <= `Ready;
rdy <= 1'b1;
end
end
`Get_Address_s_i:
state <= Get_s_i;
`Get_s_i:
state <= Calculate_j;
s_i <= rddata;
`Calculate_j:
state = Get_Address_s_j;
if (i % 3 == 2)
begin
j <= (j + s_i + key[7:0]) % 256;
end
else if (i % 3 == 1)
begin
j <= (j + s_i + key[15:8]) % 256;
end
else
begin
j <= (j + s_i + key[23:16]) % 256;
end
`Get_Address_s_j:
state <= Get_s_j;
`Get_s_j:
state <= Write_s_i;
s_j <= rddata;
`Write_s_i:
state <= Write_s_j;
`Write_s_j:
state <= Calculate_i;
`Calculate_i:
if (i < 8'd255)
begin
i <= i + 8'd1;
state <= `Get_Address_s_i;
end
else
begin
state <= `Done;
end
`Done:
rdy <= 1'b1;
state <= `Ready;
endcase
end
always_comb
begin
case(state)
`Ready:
begin
addr = 8'b0;
wrdata = 8'b0;
wren = 1'b0;
end
`Get_Address_s_i:
begin
addr = i;
wrdata = 8'b0;
wren = 1'b0;
end
`Get_s_i:
begin
addr = 8'b0;
wrdata = 8'b0;
wren = 1'b0;
end
`Calculate_j:
begin
addr = 8'b0;
wrdata = 8'b0;
wren = 1'b0;
end
`Get_Address_s_j:
begin
addr = j;
wrdata = 8'b0;
wren = 1'b0;
end
`Get_s_j:
begin
addr = 8'b0;
wrdata = 8'b0;
wren = 1'b0;
end
`Write_s_i:
begin
addr = j;
wrdata = s_i;
wren = 1'b1;
end
`Write_s_j:
begin
addr = i;
wrdata = s_j;
wren = 1'b1;
end
`Calculate_i:
begin
addr = 8'b0;
wrdata = 8'b0;
wren = 1'b0;
end
`Done:
begin
addr = 8'b0;
wrdata = 8'b0;
wren = 1'b0;
end
endcase
end
endmodule: ksa
自分で試したこと
SystemVerilog 初学者のため，全く勝手がわかっていません．基礎から時間をかけて勉強するべきなのは承知ですが，解決しないといけない課題のため，力を貸していただきたいです．よろしくお願いいいたします．
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