ISO/IEC TR 17903:2024 Information technology — Artificial intelligence — Overview of machine learning computing devices
https://www.iso.org/standard/85078.html
3 Terms and definitions
3.1 artificial intelligence computing, AI computing
processing that leverages infrastructures to enable the set of methods or automated entities that together build, optimize and apply an AI model
3.2 machine learning computing, ML computing
processing that leverages infrastructures to train and execute ML models
3.3 infrastructure
hardware and software environment to support computer system and software design, development, and modification
Note 1 to entry: Network facilities can be also infrastructure working with hardware and software. [SOURCE:ISO/IEC/IEEE 12207:2017,[1] 3.1.25, modified: note 1 to entry is added.]
3.4 computing device
functional unit (3.6) that can perform substantial computations, including numerous arithmetic operations and logic operations with or without human intervention
Note 1 to entry: A computing device can consist of a stand-alone unit (3.7), or several interconnected units. It can also be a device that provides a specific set of functions, such as a phone or a personal organizer, or more general functions such as a laptop or desktop computer.
Note 2 to entry: A computing device contains at least one unit (3.7). [SOURCE:ISO/IEC 19770-5:2015,[2] 3.6, modified: note 2 to entry is replaced.]
3.5 hardware
all or part of the physical components of an information processing system
EXAMPLE:Computers, peripheral devices.
[SOURCE:ISO/IEC 2382:2015,[3] 2121277, modified: removed note to entry 2 and 3]
3.6 functional unit
entity of hardware or software, or both, capable of accomplishing a specified purpose
Note 1 to entry: In IEC 50 (191), the more general term item is used in place of functional unit. An item may sometimes include people.[SOURCE:ISO/IEC 2382:2015, 2123022, modified: removed notes 2 and 3 to entry.]
3.7 unit
lowest level of hardware assembly for which acceptance and qualification tests are required [SOURCE:ISO 24917:2020,[4] 3.4]
3.8 service
kind of application which encapsulates one or more computing modules and can be accessed through a specified interface [SOURCE:ISO/IEC 19763-5:2015,[5] 3.1.18]
3.9 artificial intelligence computing device
AI computing device
computing device (3.4) that can be specifically used for accelerating some or all of artificial intelligence computing
Note 1 to entry: An artificial intelligence computing device often contains and works with specific enabling software.
3.10 machine learning computing device, ML computing device
computing device (3.4) that can be specifically used for accelerating machine learning computing
Note 1 to entry: A machine learning computing device often contains and works with specific enabling software.
Note 2 to entry: Machine learning computing device is a subset of AI computing device (3.9).
EXAMPLE:A neural network process unit and its associated enabling software.
3.11 performance
measurable result
Note 1 to entry: Performance can relate either to quantitative or qualitative findings.
Note 2 to entry: Performance can relate to the management of activities, processes, products (including services), systems or organizations. [SOURCE:ISO/IEC 27000:2018,[6] 3.52]
3.12 effectiveness
extent to which planned activities are realized and planned results are achieved
[SOURCE:ISO/IEC 33001:2015,[7] 3.1.3]
3.13 efficiency
resources expended in relation to the accuracy and completeness with which users achieve goals [SOURCE:ISO/IEC 25063:2014,[8] 3.4]
3.14 datatype
set of distinct values, characterized by properties of those values and by operations on those values [SOURCE:ISO/IEC 11404:2007,[9] 3.12]
3.15 operator
mathematical or logical symbol that represents an action to be performed in an operation, or a symbol representing the name of a function [SOURCE:ISO/IEC/IEEE 24765:2017,[12] 3.2716, modified — 3.2716.3 and 3.2716.4 are combined.]
3.16 schedule
methods for controlling the timing of the execution of an activity within or represented by a managed object [SOURCE:ISO/IEC 10164-15:2002,[33] 3.1.27]
3.17 topology
structure of the communication paths between the medium attachment points [SOURCE:ISO/IEC 14543-2-1:2006,[48] 3.2.30]
3.18 stream
sequence of representations of jobs or parts of jobs to be performed, as submitted to an operating system [SOURCE:ISO/IEC 2382:2015,[3] 2122886]
3.19 computing
actions performed or approaches implemented by a system, aiming at processing specific kinds of data or providing solutions to certain tasks
Note 1 to entry: Computing can also be a system providing functionalities or characteristics.
3.20 heterogeneous computing
system that uses more than one kind of processor or cores [SOURCE:ISO/IEC 30145-3:2020, 3.1.5]
3.21 distributed computing
spreading of computation and data across a number of computers connected by a network [SOURCE:ISO/IEC/IEEE 24765:2017,[12] 3.1240]
3.22 quantum computing
use of quantum phenomena for computational purposes [SOURCE:ISO/TS 80004-12:2016, 6.5]
3.23 cloud computing
paradigm for enabling network access to a scalable and elastic pool of shareable physical or virtual resources with self-service provisioning and administration on-demand
Note 1 to entry: Examples of resources include servers, operating systems, networks, software, applications and storage equipment. [SOURCE:ISO/IEC 22123-1:2021, 3.2.1]
3.24 inter-cloud computing
paradigm for enabling the interworking between two or more cloud service providers [SOURCE:ISO/IEC 22123-1:2021, 3.12.1]
3.25 edge computing
distributed computing in which processing and storage takes place at or near the edge, where the nearness is defined by the system's requirements [SOURCE:ISO/IEC TR 23188:2020, 3.1.3]
3.26 processing
run of an algorithm, treatment on data or a sequence of them performed by AI systems
3.27 buffer
device or storage area used to store data temporarily to compensate for differences in rates of data flow, time of occurrence of events, or amounts of data that can be handled by the devices or processes involved in the transfer or use of the data[SOURCE:ISO/IEC/IEEE 24765:2017,[12] 3.430.1]
3.28 cache
temporary storage in computer memory, to improve operations by having frequently used data readily available for retrieval [SOURCE:ISO/IEC/IEEE 24765:2017,[12] 3.452.1]
Bibliography
[1] ISO/IEC/IEEE 12207:2017, Systems and software engineering — Software life cycle processes
[2] ISO/IEC 19770-5:2015, Information technology — IT asset management — Overview and vocabulary — Part 5: Overview and vocabulary
[3] ISO/IEC 2382:2015, Information technology — Vocabulary
[4] ISO 24917:2020, Space systems — General test requirements for launch vehicles
[5] ISO/IEC 19763-5:2015, Information technology — Metamodel framework for interoperability (MFI) — Part 5: Metamodel for process model registration
[6] ISO/IEC 27000:2018, Information technology — Security techniques — Information security management systems — Overview and vocabulary
[7] ISO/IEC 33001:2015, Information technology — Process assessment — Concepts and terminology
[8] ISO/IEC 25063:2014, Systems and software engineering — Systems and software product Quality Requirements and Evaluation (SQuaRE) — Common Industry Format (CIF) for usability: Context of use description
[9] ISO/IEC 11404:2007, Information technology — General-Purpose Datatypes (GPD)
[10] IEEE 754, Standard for Floating-Point Arithmetic
[11] Devlin Jacob et al., Bert: Pre-training of deep bidirectional transformers for language understanding. NAACL-HLT. 2019, 1, 4171-4186.
[12] ISO/IEC/IEEE 24765:2017, Systems and software engineering — Vocabulary
[13] García José et al., Enhancing a machine learning binarization framework by perturbation operators: analysis on the multidimensional knapsack problem. International Journal of Machine Learning and Cybernetics. 2020, 11(9), 1951-1970. doi:10.1007/s13042-020-01085-8
[14] Crespo José, Montáns Francisco Javier, Fractional Mathematical Operators and Their Computational Approximation. Mathematical Problems in Engineering. 2016, 4356371, 1-12. doi: 10.1155/2016/4356371
[15] Cowan M. et al., Automating generation of low precision deep learning operators. arXiv preprint. arXiv:1810.11066. 2018.
[16] Zhang X. et al., Predoo: precision testing of deep learning operators. Proceedings of the 30th ACM SIGSOFT International Symposium on Software Testing and Analysis. 400-412. 2021.
[17] Cheng X. et al., HAFLO: GPU-Based Acceleration for Federated Logistic Regression. arXiv preprint. arXiv:2107.13797. 2021.
[18] NVIDIA Corporation & affiliates. CUDA C++ Programming Guide. CUDA C++ Programming Guide [online]. U.S., California, 23 August 2023 [viewed 20 September 2023]. Available from: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html
[19] HUAWEI Technologies CO, Ltd. CANN Community Edition. CANN Community[online]. CN, Guangdong, 18 September 2023 [viewed 20 September 2023]. Available from: https://www.hiascend.com/software/cann/community
[20] Intel Corporation, oneAPI Programming Model. oneAPI Programming Guide[online]. U.S., California, 14 July 2023 [viewed 20 September 2023]. Available from: https://www.intel.com/content/www/us/en/docs/oneapi/programming-guide/2023-2/overview.html
[21] i2tutorials. TensorFlow Operators. TensorFlow Tutorial[online]. India, Banglore, 20 April 2023 [viewed 20 September 2023]. Available from: https://www.i2tutorials.com/tensorflow-tutorial/tensorflow-operators/
[22] PyTorch Contributors, Named Tensors operator coverage. The Linux Foundation Pytorch Docs [online]. U.S., State of Oregon, 15 Mar 2023 [viewed 20 September 2023]. Available from: https://pytorch.org/docs/stable/name_inference.html
[23] HUAWEI Technologies CO, Ltd. MindSpore Operator List. HUAWEI MindSpore Community[online]. CN, Guangdong, 12 July 2023 [viewed 20 September 2023]. Available from: https://www.mindspore.cn/doc/note/en/r1.0/operator_list_ms.html
[24] Contributors M.L.I.R., Multi-Level Intermediate Representation Overview. Multi-Level IR Compiler Framework [online]. U.S., State of Illinois, 22 August 2023 [viewed 20 September 2023]. Available from: https://mlir.llvm.org/
[25] The Linux Foundation, The open standard for machine learning interoperability. Open Neural Network Exchange [online] U.S., State of Oregon, 6 March 2023 [viewed 20 September 2023]. Available from: https://onnx.ai/
[26] Khronos Group, The OpenCL Specification 3.0. Khronos OpenCL Working Group[online]. U.S., State of Oregon, 17 April 2023 [viewed 20 September 2023]. Available from: https://www.khronos.org/registry/OpenCL/specs/3.0-unified/pdf/OpenCL_API.pdf
[27] Ahmad A.B.D.E.L.F.A.T.T.A.H. et al., MAGMA 2.7.2. MAGMA[online]. U.S., Tennessee, 25 August 2023 [viewed 20 September 2023]. Available from: https://github.com/kjbartel/clmagma
[28] Panda Preeti Ranjan, Dutt Nikil D., Nicolau Alexandru, On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Transactions on Design Automation of Electronic Systems (TODAES). 2000, 5(3), 682-704. doi:10.1145/348019.348570
[29] Cong J. et al., Bandwidth optimization through on-chip memory restructuring for HLS. The 54th ACM/EDAC/IEEE Design Automation Conference. 1-6. IEEE. 2017.
[30] Park J., Sung W., FPGA based implementation of deep neural networks using on-chip memory only. 2016 IEEE International conference on acoustics, speech and signal processing (ICASSP). 1011-1015. IEEE, 2016.
[31] Li H. et al., On-chip memory technology design space explorations for mobile deep neural network accelerators. 2019 56th ACM/IEEE design automation conference (DAC). 1-6. IEEE. 2019.
[32] NVIDIA Corporation & affiliates. Solution Overview. NVIDIA DGX Platform The best of NVIDIA AI—all in one place [online]. U.S., California, March 2023 [viewed 20 September 2023]. Available from: https://resources.nvidia.com/en-us-dgx-platform/nvidia-dgx-platform-solution-overview-web-us
[33] ISO/IEC 10164-15:1995, Information technology — Open Systems Interconnection — Systems Management: Scheduling function
[34] Mirmahaleh Seyedeh Yasaman Hosseini et al., Data scheduling and placement in deep learning accelerator. Cluster Computing. 2021, 24(4), 3651-3669. doi:10.1007/s10586-021-03355-8
[35] Giorgi Roberto, Scionti Alberto, A scalable thread scheduling co-processor based on data-flow principles. Future Generation Computer Systems. 2015, 53, 100-108. doi:10.1016/j.future.2014.12.014
[36] Raveendran A. et al., RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. International Symposium on VLSI Design and Test. 1066, 482-495. Springer. 2019.
[37] Rivas-Gomez S. et al., Exploring the vision processing unit as co-processor for inference. 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). 589-598. IEEE, 2018.
[38] Akgün G., Göhringer D., Power-Aware Real-Time Operating Systems on Reconfigurable Architectures. 2021 31st International Conference on Field-Programmable Logic and Applications (FPL). 402-403. IEEE, 2021.
[39] Poluri Pavan, Louri Ahmed, Shield: A reliable network-on-chip router architecture for chip multiprocessors. IEEE Transactions on Parallel and Distributed Systems. 2016, 27(10), 3058-3070. doi: 10.1109/TPDS.2016.2521641
[40] Hagiwara Kesami et al., A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. 2018 IEEE symposium in low-power and high-speed chips (COOL CHIPS). 1-3. IEEE. 2018
[41] He K. et al., Deep residual learning for image recognition. Proceedings of the IEEE conference on computer vision and pattern recognition. 770-778. IEEE. 2016.
[42] Yang Wangdong, Li Kenli, Li Keqin, A pipeline computing method of SpTV for three-order tensors on CPU and GPU. ACM Transactions on Knowledge Discovery from Data (TKDD). 2019, 13(6), 1-27. doi:10.1145/3363575
[43] Mohanty P.K. et al., Implementation of cubic spline interpolation on parallel skeleton using pipeline model on CPU-GPU cluster. 2016 IEEE 6th International Conference on Advanced Computing (IACC). 747-751. IEEE, 2016.
[44] Chrysogelos P. et al., HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines. Proc. VLDB Endow. 12, 544-556. 2019.
[45] Li Zhifang, Peng Beicheng, Weng Chuliang, XeFlow: Streamlining Inter-Processor Pipeline Execution for the Discrete CPU-GPU Platform. IEEE Transactions on Computers. 2020, 69(6), 819-831. doi: 10.1109/TC.2020.2968302
[46] Xiang Y., Kim H., Pipelined data-parallel CPU/GPU scheduling for multi-DNN real-time inference. 2019 IEEE Real-Time Systems Symposium (RTSS). 392-405. IEEE, 2019
[47] Chen C.C., Yang C.L., Cheng H.Y., Efficient and robust parallel dnn training through model parallelism on multi-gpu platform. arXiv preprint. arXiv:1809.02839, 2018
[48] ISO/IEC 14543-2-1:2006, Information technology - Home electronic systems (HES) architecture — Part 2-1: Introduction and device modularity
[49] Martínez-Frutos Jesús, Martínez-Castejón Pedro J., Herrero-Pérez David, Efficient topology optimization using GPU computing with multilevel granularity. Advances in Engineering Software. 2017, 106, 47-62. doi:10.1016/j.advengsoft.2017.01.009
[50] Sotiropoulos Stefanos, Kazakis Georgios, Lagaros Nikos D., High performance topology optimization computing platform. Procedia Manufacturing 44, 441-448. 2020
[51] Mirmahaleh S.Y.H. et al., Flow mapping and data distribution on mesh-based deep learning accelerator. Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip. 1-8. 2019.
[52] Firuzan A. et al., Reconfigurable network-on-chip for 3D neural network accelerators. 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS). 1-8. IEEE. 2018.
[53] Zou Kaiwei et al., Learn-to-scale: Parallelizing deep learning inference on chip multiprocessor architecture. Design, Automation & Test in Europe Conference & Exhibition (DATE). 1172-1177. IEEE. 2019.
[54] Scionti Alberto, Mazumdar Somnath, Portero Antoni, Towards a scalable software defined network-on-chip for next generation cloud. Sensors. 2018, 18(7), 23-30. doi:10.3390/s18072330
[55] Tallent N.R. et al., Evaluating on-node gpu interconnects for deep learning workloads. International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems. 8, 3-21. Springer. 2017.
[56] Gawande Nitin A. et al., Scaling deep learning workloads: Nvidia dgx-1/pascal and intel knights landing. Future Generation Computer Systems 108, 1162-1172. 2020.
[57] Zhao H. et al., HiveD: Sharing a GPU Cluster for Deep Learning with Guarantees. 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20). 515-532. 2020.
[58] Luitjens J., CUDA Streams – Best practices and common pitfalls. GPU Technology Conference [online]. U.S., California, 26 March 2014 [viewed 20 September 2023]. Available from: https://on-demand.gputechconf.com/gtc/2014/presentations/S4158-cuda-streams-best-practices-common-pitfalls.pdf
[59] Zhang F. et al., FineStream: Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated Architectures. 2020 USENIX Annual Technical Conference (USENIX ATC 20). 633-647. 2020.
[60] Wang L. et al., Blasx: A high performance level-3 blas library for heterogeneous multi-gpu computing. Proceedings of the 2016 International Conference on Supercomputing. 20, 1-11. 2016.
[61] Cheng J., Zhao K., Xu Y., Global-view based Task Migration for Deep Learning Processor. 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking. 908-915. IEEE, 2021.
[62] Dhakal A., Kulkarni S.G., Ramakrishnan K.K., Machine learning at the edge: Efficient utilization of limited cpu/gpu resources by multiplexing. 2020 IEEE 28th International Conference on Network Protocols (ICNP). 1-6. IEEE. 2020.
[63] Mills Richard Tran et al., Toward performance-portable PETSc for GPU-based exascale systems. Parallel Computing. 2020, 108, 102831. doi:10.1016/j.parco.2021.102831
[64] ISO/IEC 15045-2, Information technology — Home Electronic System (HES) gateway — Part 2: Modularity and protocol
[65] ISO/IEC 18012-2, Information technology — Home Electronic System — Guidelines for product interoperability — Part 2: Taxonomy and application interoperability model
[66] ISO/IEC/IEEE 9945, Information technology — Portable Operating System Interface (POSIX®) Base Specifications, Issue 7
[67] ISO/IEC 23007-1, Information technology — Rich media user interfaces — Part 1: Widgets
[68] ISO/IEEE 11073-10422, Health informatics — Personal health device communication — Part 10422: Device specialization — Urine analyser
[69] IEC 80004-9, Nanotechnologies — Vocabulary — Part 9: Nano-enabled electrotechnical products and systems
[70] ISO/IEC 19944-1, Cloud computing and distributed platforms ─ Data flow, data categories and data use — Part 1: Fundamentals
[71] ISO/IEC 19505-1, Information technology — Object Management Group Unified Modeling Language (OMG UML) — Part 1: Infrastructure
[72] ISO 15531-1, Industrial automation systems and integration — Industrial manufacturing management data — Part 1: General overview
[73] Gholami Amir et al., A survey of quantization methods for efficient neural network inference. Low-Power Computer Vision. Chapman and Hall/CRC. 2022, 291-326. doi: 10.1201/9781003162810-13
[74] ISO 10795, Space systems — Programme management and quality — Vocabulary
[75] ISO 22166-1, Robotics — Modularity for service robots — Part 1: General requirements
[76] ISO 9000, Quality management systems — Fundamentals and vocabulary
[77] ISO/IEC 19763-5, Information technology — Metamodel framework for interoperability (MFI) — Part 5: Metamodel for process model registration
[78] ISO/TR 12773-2, Business requirements for health summary records — Part 2: Environmental scan
[79] ISO/IEEE 11073-20702, Health informatics — Point-of-care medical device communication — Part 20702: Medical devices communication profile for web services
[80] ISO 26000, Guidance on social responsibility
[81] ISO 19145:2013, Geographic information — Registry of representations of geographic point location
[82] ISO/IEC/IEEE 15939, Systems and software engineering — Measurement process
[83] ISO/IEC 24752-8, Information technology — User interfaces — Universal remote console — Part 8: User interface resource framework
[84] ISO/IEC/TR 30109, Information technology — User interfaces — Worldwide availability of personalized computer environments
[85] ISO 22902-1, Road vehicles — Automotive multimedia interface — Part 1: General technical overview
[86] ISO 27501, The human-centred organization — Guidance for managers
[87] ISO 13372, Condition monitoring and diagnostics of machines — Vocabulary
[88] Xu D., Xu M., Wang Q. et al., Mandheling: Mixed-precision on-device dnn training with dsp offloading. Proceedings of the 28th Annual International Conference on Mobile Computing And Networking. 214-227. 2022
[89] Micikevicius P., Narang S., Alben J., Diamos G., Elsen E., Garcia D., Wu, H. Mixed precision training. ICLR. 2018
[90] ISO/IEC 5212, Information technology — Data usage — Guidance for data usage
[91] ISO/IEC 11179-1, Information technology — Metadata registries (MDR) — Part 1: Framework
[92] ISO/IEC 11179-30, Information technology — Metadata registries (MDR) — Part 30: Basic attributes of metadata
[93] ISO/IEC 19763-1, Information technology — Metamodel framework for interoperability (MFI) — Part 1: Framework
[94] ISO/IEC 19763-3, Information technology — Metamodel framework for interoperability (MFI) — Part 3: Metamodel for ontology registration
[95] ISO/IEC 8183, Information technology — Artificial intelligence — Data life cycle framework
[96] ISO/IEC 5259-1:—,1 Artificial intelligence — Data quality for analytics and machine learning (ML) — Part 1: Overview, terminology, and examples
[97] Zheng C., Zong B., Cheng W., Song D., Ni J., Yu W, Wang W., Robust graph representation learning via neural sparsification. International Conference on Machine Learning. 11458-11468. PMLR. 2020
[98] Giladi R., Ahitav N., SPEC as a performance evaluation measure. Computer, 28(8), 33-42. 1995
[99] ISO/IEC 30134-2, Information technology — Data centres — Key performance indicators — Part 2: Power usage effectiveness (PUE)
[100] ISO/IEC/TS 4213, Information technology — Artificial intelligence — Assessment of machine learning classification performance
[101] IEEE 2937, Standard for Performance Benchmarking for Artificial Intelligence Server Systems
[102] ISO/IEC 16350, Information technology — Systems and software engineering — Application management
[103] ISO/IEC 30145-3, Information technology — Smart City ICT reference framework — Part 3: Smart city engineering framework
ChatGPT
About ISO/IEC TR 17903:2024 Information technology — Artificial intelligence — Overview of machine learning computing devices https://qiita.com/kaizen_nagoya/items/975c330fd00d3a2a677e, Please explain the purpose and achievements of the standard, as well as any omissions and challenges, from the three perspectives of those who build AI, those who use it, and other third parties.
Purpose & Achievements
Purpose
As per the ISO/IEC website, the TR is described thus:
“This document surveys machine learning (ML) computing devices, including the following: — ML computing device terminology and characteristics; — existing approaches to the setting and use of characteristics for optimizing ML computing device performance. The information provided in this document is relevant for organizations of all types and sizes.”
ISO+1
So its high-level aims are:
To establish a shared vocabulary / terminology around ML computing devices (hardware + enabling software) in the context of AI/ML.
Qiita+1
To catalogue / characterise the attributes (characteristics) of ML computing devices — e.g., datatypes, memory access, scheduling, topology, streams, buffers, caches, data exchange, etc.
スタンダーズオーストラリアストア+1
To summarise existing approaches for optimising performance of ML computing devices (i.e., how hardware + enabling software trade-offs are handled, resource management, scheduling, heterogeneous computing, etc.)
cdn.standards.iteh.ai+1
To act as a generic, organisation-agnostic resource (for all sizes/types of organisations) for understanding what “ML computing device” means and what to look out for.
Evs+1
Achievements
From what we can glean:
Terminology consolidation — The TR defines ML computing device, AI computing device, infrastructure, functional unit, etc. (e.g., clauses 3.1–3.11) in the Qiita article.
Qiita
This helps reduce ambiguity when people talk about “accelerators”, “ML operators”, “heterogeneous computing”, “edge computing”, etc.
Mapping of characteristics — Section 6 in the TR (according to the summary) sets out characteristics (datatypes, operators, memory access/ addressing mechanisms, scheduling, topology, streams, buffering, cache, data exchange) each with “general” and “effectiveness/efficiency” sub-clauses.
スタンダーズオーストラリアストア+1
This gives practitioners a checklist of device characteristics to consider or compare.
Performance-optimisation approaches — The TR includes section 7 (Approaches and measures for performance optimisation) which covers e.g., computing resource-level, enabling software-level, and measures.
スタンダーズオーストラリアストア
For organisations designing or procuring ML computing devices, this helps highlight what “good” looks like in terms of efficiency and resource usage.
Bridging hardware/software gap — While many standards focus either on ML algorithmic aspects, system architecture, or software frameworks, this TR explicitly addresses the device (hardware + enabling software) dimension of ML — which is relatively under-covered. For builders/manufacturers of accelerators, or users provisioning ML infrastructure, this helps align language.
Supporting ecosystem of AI standards — The TR sits among a family of ISO/IEC AI standards (e.g., terminology, frameworks, data quality, risk management) and helps fill the gap of “computing device” view in the AI chain. As noted in the Qiita article, the TR is among newer ones in the 2023-2025 time-frame.
IEC
From the perspective of each stakeholder group, the above achievements mean:
Builders/manufacturers: A clearer target of what to deliver (device characteristics, efficiency measures), a form of benchmark vocabulary to communicate with users.
Users/deployers: Better ability to compare devices (via characteristics), make more informed procurement decisions, understand what to expect from device performance.
Third parties (auditors/regulators/standard-adopters): More standardised language to evaluate claims from manufacturers, more clarity about what “ML computing device performance” means, potential basis for auditing or procurement specifications.
Omissions & Challenges
Despite its contributions, there are also omissions, limitations and open challenges. I’ll discuss them and link them to the stakeholder perspectives.
For Builders / Manufacturers
Omissions / Challenges
Lack of prescriptive metrics or thresholds — The TR surveys characteristics and optimisation approaches, but it does not define fixed performance thresholds, normative benchmarks, or detailed test methods (at least as it appears). It is a Technical Report not a full Standard, and is represented as “surveying” rather than “requiring”.
ISO +1
For builders wanting “what is minimally acceptable” or “what do I have to certify against”, this may be less helpful.
Rapidly evolving hardware/software space — ML accelerators, heterogenous computing, specialised AI chips, edge devices, memory architectures, software frameworks (e.g., ML compilers) are evolving very fast. A snapshot survey may quickly become out-of-date. Builders will need to track evolution and the TR may not keep pace with future novel architectures (e.g., neuromorphic, photonic, quantum-ML). Indeed the TR mentions quantum computing and heterogeneous computing definitions.
Qiita
Implementation specificity missing — The TR describes “characteristics” and “existing approaches”, but may not provide deep guidance on how to implement or validate them in device design – e.g., actual micro-architecture trade-offs, manufacturing cost, power/thermal constraints, end-to-end ML training/inference use-cases. That means builders still must rely on proprietary or domain-specific know-how.
Ecosystem interdependencies — The performance of ML computing devices is heavily influenced by software frameworks (compilers, runtimes), model architectures, data movement, system integration, and end-to-end workflows. The TR touches on enabling software but may not deeply address the full system stack or integration issues (e.g., how device characteristics map to ML model accuracy, latency, energy efficiency in real workflows). Builders must still navigate system‐level complexity.
Emerging concerns like sustainability, lifecycle, supply chain — While the TR addresses “efficiency” and resource use, it may not comprehensively cover environmental/sustainability metrics (e.g., carbon footprint of device manufacturing/operation across life-cycle), or supply-chain traceability of specialised accelerators, which are growing concerns.
Implications
Builders may use the TR as a framing document, but cannot treat it as a full specification for product certification.
Risk of “bibliographic compliance” (saying “we follow TR 17903”) without deeper internal technical validation.
Device vendors may diverge in interpretations of the “characteristics” and “optimisation approaches”, leading to inconsistent implementation.
For Users / Deployers
Omissions / Challenges
Gap between device-spec and system outcome — Users may see device characteristics (datatype support, memory access, topology) but the TR may not clearly translate these into system-level outcomes they care about: e.g., how many images/second, training/inference latency for their model, cost/performance for their workload, energy usage in their environment. Thus procurement decisions still require significant internal benchmarking and workload profiling.
Workload and domain specificity — ML workloads vary widely (computer vision, NLP, reinforcement learning, edge IoT, federated learning). The TR offers general device characteristics, but users will still need to map those to their specific models and domains. The TR may not provide domain-specific guidance on which device features matter most.
Integration and end-to-end systems — Device alone is one piece; the user must consider data pipelines, model training, inference, model updates, edge vs cloud, system deployment, lifecycle. The TR touches the computing device but may not fully address deployment environment or operational concerns (e.g., model drift, updating hardware, edge deployment constraints).
Obsolescence and upgrade path — As hardware evolves fast, users may struggle to know when/how to upgrade, and how device characteristics future-proof their deployment. The TR being a survey means it may not give strategic guidance.
Cost, procurement, vendor claims — Users still face challenges parsing vendor claims, benchmarking results, vendor lock-in, and cost trade-offs (capital expenditure, operational expenditure, energy costs). The TR provides characteristic lists but not cost/benefit frameworks.
Transparency and comparability — Although device characteristics are defined, vendors may not publish consistent metrics; there may still be lack of standardised benchmarking, and thus still difficulties for users to compare apples-to-apples.
Implications
Users should treat the TR as a useful reference/checklist but still perform independent benchmarking and domain-specific evaluation.
They should ask vendors for metrics aligned to the characteristics in the TR (e.g., datatype support, memory access mechanisms, scheduling, etc.).
Users should pair device metrics with workload-specific measures (latency, throughput, power, cost) and not rely solely on vendor spec sheets.
For Third Parties (Auditors / Regulators / Standard-Adopters)
Omissions / Challenges
Non-normative nature — As a “Technical Report” (TR) rather than a normative “Standard” (IS), the document may not establish mandatory requirements. For auditors or regulators seeking enforceable compliance, this may limit its role. It provides useful guidance but not necessarily binding measures.
Lack of test/benchmark method detail — For auditing/compliance, one often needs standardised test protocols, measurement methods, traceability. The TR seems to survey existing approaches rather than set a standard test suite. That means third parties may still need to develop or rely on additional standards for measurement, benchmarking, certification.
Rapid technological change and heterogeneity — Third parties evaluating devices in an ecosystem with diverse hardware/software stacks may find that the TR’s generality leaves many grey areas (e.g., what exactly qualifies as “heterogeneous computing”, how to assess “effectiveness/efficiency” of memory access across different vendor architectures). It may permit broad interpretation which challenges comparability across audits.
Context beyond device — For regulators or standard-adopters concerned with AI trustworthiness, safety, fairness, transparency, supply chain, environmental impact, etc., the TR focuses on computing device characteristics and optimisation for ML performance — which is only one dimension of the broader AI systems ecosystem. Third parties may need to reference other standards to cover those aspects (e.g., data quality, risk management, lifecycle governance).
Global alignment / regionalisation issues — As device manufacturing and supply chains are global, third parties may struggle with regional differences in regulation, terminologies, or proprietary vendor claims. The TR helps unify terminology but enforcement across multiple geographies may still be uneven.
Implications
Auditors and regulators can use the TR as an informative reference to shape checklists and evaluation frameworks, but may need to incorporate additional normative standards and detailed measurement protocols.
Standard-adopters (companies adopting standards proactively) can align their hardware procurement spec and vendor contracts with the vocabulary and characteristics in the TR, but must still build their own internal compliance/verification approaches.
Summary Table
Here’s a summary table pulling the three perspectives together:
Stakeholder Achievements / Benefits Omissions / Challenges
Builders/Manufacturers Shared vocabulary; clearer device characteristic checklist; highlighting performance-optimisation approaches; bridging hardware/software gap. No prescriptive metrics; fast-moving hardware/software means risk of obsolescence; limited implementation detail; full system integration not covered; sustainability/supply-chain concerns less emphasised.
Users/Deployers Helps compare devices; improves procurement language; aids in understanding device features and trade-offs. Device spec ↔ real workload gap; domain-specific mappings needed; integration & lifecycle concerns; upgrade path unclear; cost/benefit analyses still needed; vendor claims still variable.
Third Parties (Auditors/Regulators) Useful reference for checklists and vocabulary; helps structure evaluation of devices; aids standard-adoption frameworks. Non-normative nature (TR not full standard); lacks measurement/test protocols; broadness leads to ambiguity; doesn’t cover full AI system issues (safety, fairness, data, lifecycle); global/regional enforcement issues.
Additional Considerations from the Qiita Article
The Qiita article by Dr. Kiyoshi Ogawa (kaizen_nagoya) highlights some further points (in somewhat Japanese-engineering context) worthy of mention:
It underlines that the TR clarifies that a machine-learning computing device (ML computing device) is a subset of AI computing device. For example: “A computing device (3.4) that can be specifically used for accelerating machine learning computing”.
Qiita
The article also emphasises the TR’s breakdown of “characteristics” (Section 6) and the classification of “effectiveness” vs “efficiency” in each characteristic (e.g., memory access & addressing mechanisms: general + effectiveness/efficiency) which is helpful for comparing devices in design or procurement.
Qiita
It draws attention to the fact that the TR is quite short (≈25 pages) and high-level, meaning it is an overview rather than an in-depth engineering manual. This matches the “survey” nature of the document.
The article suggests that for many engineers or architects working on ML accelerators or device selection, the TR helps get common language but emphasises that deeper vendor/benchmark information will still be needed in practice.
Concluding Thoughts
In summary: ISO/IEC TR 17903:2024 is a welcome addition to the AI standards ecosystem. It provides a much-needed treatment of the “computing device” layer of ML systems, offering a vocabulary and characteristic framework that helps builders, users and third parties better articulate and assess ML hardware/software. However, it is by design a survey/overview document, and thus cannot substitute for detailed device specification standards, measurement/test frameworks, or system-level deployment guidance. Stakeholders will benefit if they use it as a reference layer, paired with domain-specific evaluation, vendor benchmarking, and complementary standards (e.g., for data quality, risk management, AI system lifecycle).
If you like, I can check specific sections of the TR (e.g., Section 6 and 7) and map them to real-world device selection or ML system procurement — would you like me to do that?
Ref.
ISO IEC Artificial intelligence Standards
https://qiita.com/kaizen_nagoya/items/1d1ffe4ac8e1dc67501f
大規模言語モデル講座 基礎編 2025 Autumn 敗因を勝因に
https://qiita.com/kaizen_nagoya/items/34ffd2b0c47a5f3665d9
MCP入門 〜面倒なことはAIエージェントにやらせよう〜 by からあげ を聞きながら
https://qiita.com/kaizen_nagoya/items/54b648c838fae8d57e38
MCP入門 〜面倒なことはAIエージェントにやらせよう〜 by からあげ を聞きながら、補足と反論 by ChatGPT
https://qiita.com/kaizen_nagoya/items/0939d58d31666562090c
C言語を習得する３つの方法
https://qiita.com/kaizen_nagoya/items/84cab0888c193bba429b
Views上位６４記事 20250617現在
https://qiita.com/kaizen_nagoya/items/26dbbd04cf18b7742972
C言語(C++)が必要な人、必要ない人 with ChatGPT
https://qiita.com/kaizen_nagoya/items/a074cb8cd292d8d94bd4
C言語を習得する３つの方法 with ChatGPT
https://qiita.com/kaizen_nagoya/items/4a3518a18fa49f46787f
＜この記事は個人の過去の経験に基づく個人の感想です。現在所属する組織、業務とは関係がありません。＞
This article is an individual impression based on my individual experience. It has nothing to do with the organization or business to which I currently belong.
Este artículo es una impresión personal basada en mi experiencia personal. No tiene nada que ver con la organización o empresa a la que pertenezco actualmente.
文書履歴(document history)
ver. 0.01 初稿 20251016
最後までおよみいただきありがとうございました。
いいね 💚、フォローをお願いします。
Thank you very much for reading to the last sentence.
Please press the like icon 💚 and follow me for your happy life.
Muchas gracias por leer hasta la última oración.
Por favor, haz clic en el ícono Me gusta 💚 y sígueme para tener una vida feliz.