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- Masahiro Kawano@kawanon868
高専→大学→大学院→社会人5年目 主に時刻同期関連のFPGA開発やってます
- Dr. Kiyoshi Ogawa@kaizen_nagoya
I'm a network designer.I work on TOPPERS SmallestSetProfile Kernel,MISRA-C/C++, STARC RTL Design StyleGuide (Verilog-HDL), and HAZOP.I was an editor of ISO/IEC 15504.
