オンラインデモ

オンラインのデモがあるので試してみます.

//----------------------------------------------------------------------------//
// Generated by LegUp High-Level Synthesis Tool Version 3.0 (http://legup.org)
// Compiled: Mon Jan 21 17:30:53 2013
// University of Toronto
// For research and academic purposes only. Commercial use is prohibited.
// Please send bugs to: legup@eecg.toronto.edu
// Date: Thu May 15 04:18:39 2014
//----------------------------------------------------------------------------//

`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 64
// Number of RAM elements: 4
`define MEMORY_CONTROLLER_TAG_SIZE 9
`define TAG_NULL `MEMORY_CONTROLLER_TAG_SIZE'd0
`define TAG_PROCESSOR `MEMORY_CONTROLLER_TAG_SIZE'd1
// @.str = private unnamed_addr constant [8 x i8] c"default\00"

`define TAG_g__str `MEMORY_CONTROLLER_TAG_SIZE'd3
`define TAG_g__str_a {`TAG_g__str, 23'b0}
// @imem = internal unnamed_addr constant [44 x i32] [i32 -1885077504, i32 665124868, i32 614858756, i32 266368, i32 12726305, i32 202375190, i32 0, i32 872546314, i32 12, i32 1006702593, i32 875036672, i32 280704, i32 17385505, i32 -1926627328, i32 350336, i32 17520673, i32 -1922301952, i32 25847850, i32 295698435, i32 -1389625344, i32 -1385562112, i32 65011720, i32 666763252, i32 -1346437112, i32 -1347354620, i32 -1347420160, i32 605028352, i32 705167368, i32 285212683, i32 638648321, i32 707264520, i32 285212678, i32 637796352, i32 639959040, i32 202375177, i32 640745473, i32 135266334, i32 638582785, i32 135266331, i32 -1883308024, i32 -1884225532, i32 -1884291072, i32 666697740, i32 65011720], align 4

`define TAG_g_imem `MEMORY_CONTROLLER_TAG_SIZE'd2
`define TAG_g_imem_a {`TAG_g_imem, 23'b0}
//   %dmem = alloca [64 x i32], align 4
`define TAG_main_0_dmem `MEMORY_CONTROLLER_TAG_SIZE'd5
`define TAG_main_0_dmem_a {`TAG_main_0_dmem, 23'b0}
//   %reg = alloca [32 x i32], align 4
`define TAG_main_0_reg `MEMORY_CONTROLLER_TAG_SIZE'd4
`define TAG_main_0_reg_a {`TAG_main_0_reg, 23'b0}

// Turn off warning 'ignoring unsupported system task'
// altera message_off 10175

module top
	(
		clk,
		reset,
		start,
		finish,
		return_val
	);
input clk;
input reset;
input start;
output wire finish;
output wire [31:0] return_val;
wire memory_controller_waitrequest;
wire memory_controller_enable_a;
...

なにやら Verilog コードが無事に吐かれました. 素晴らしいですね!