WEB: Pyton, JavaScript, Ruby on Rails FPGA: Verilog HDL
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- Dr. Kiyoshi Ogawa@kaizen_nagoya
I'm a network designer.I work on TOPPERS SmallestSetProfile Kernel,MISRA-C/C++, STARC RTL Design StyleGuide (Verilog-HDL), and HAZOP.I was an editor of ISO/IEC 15504.
- SHUN Y@sy_125
Web テクニカルディレクター、フロントエンドエンジニア
