micropythonでshrike-lite その41

概要

micropythonでshrike-lite、やってみた。
uartのオウム返しやってみた。
嵌った。
テストベンチで動くのに、実機で動かない。

テストベンチ結果

結論

mycropythonがuart受信するとき、以下が必要。

reset_pin = Pin(2, Pin.OUT, value = 1)
reset_pin.value(1)
time.sleep(1)
reset_pin.value(0)
time.sleep(1)

サンプルコード

(* top *) module top #(parameter CLK = 50_000_000, parameter BAUD_RATE = 115200) (
    (* iopad_external_pin, clkbuf_inhibit *) input clk,
    (* iopad_external_pin *) output clk_en,
    (* iopad_external_pin *) input rst,
    (* iopad_external_pin *) input rx,
    (* iopad_external_pin *) output tx,
    (* iopad_external_pin *) output tx_en,
    (* iopad_external_pin *) output led,
	(* iopad_external_pin *) output led_en

);
	reg run;
	reg flag;
	wire [7:0] data;
	wire data_valid;
	wire done;
	assign clk_en = 1'b1;
	assign tx_en = 1'b1;
	assign led_en = 1'b1;
	assign led = data_valid;
	uart_rx #(.CLK(CLK), .BAUD_RATE(BAUD_RATE))
		ur (.i_Clock(clk), .i_RX_Serial(rx), .o_RX_DV(data_valid), .o_RX_Byte(data));
	uart_tx #(.IN_CLK_HZ(CLK), .DATA_FRAME(8), .BAUD_RATE(BAUD_RATE), .OVERSAMPLING_MODE(16), .STOP_BIT(1), .LSB(1'b0))
		ut (.i_clk(clk), .i_rst(rst), .o_tx(tx), .i_tx_data(data), .i_tx_start(data_valid), .o_tx_done(done));
endmodule

main.py

from machine import UART, Pin
import time
import shrike

shrike.reset()
shrike.flash("uart+.bin")

reset_pin = Pin(2, Pin.OUT, value = 1)
reset_pin.value(1)
time.sleep(1)
reset_pin.value(0)
time.sleep(1)

uart = UART(0, baudrate = 115200, tx = Pin(0), rx = Pin(1))


print("port open")

def test1():
	user_input = input()
	value = int(user_input)
	uart.write(bytes([value]))
	time.sleep(0.5)
	if uart.any():
		reply = uart.read(1)[0]
		print(reply)

def send():
	value = 49
	uart.write(bytes([value]))

def recv():
	if uart.any():
		cmd = uart.read(1)[0]
		print(cmd);

def recv_wait(timeout_ms=1000):
	start = time.ticks_ms()
	while time.ticks_diff(time.ticks_ms(), start) < timeout_ms:
		if uart.any():
			cmd = uart.read(1)[0]
			print(f"Received: {cmd}")
			return
	print("Timeout: No data received")


def test():
	send()
	time.sleep(0.05)
	recv()

def test2():
	send()
	time.sleep(0.05)
	recv_wait()

実行結果

>shrike0
Port open ok



>>>
test()
>>> test()
49

写真

テストベンチ

`timescale 1ns / 1ps

module test_tb;
	parameter CLK_FREQ_HZ = 50_000_000;
	parameter BAUD_RATE = 115_200;
	localparam CLK_PER = 20;
	localparam BIT_PERIOD = 1_000_000_000 / BAUD_RATE;
	reg clk = 0;
	reg rst = 0;
	reg [7:0] rx_read_val;
	wire tx;
	reg rx = 1'b1;
	wire tx_en,
		clk_en;
	integer i;
	integer j;
	task send_serial_byte(input [7:0] data_byte);
		begin
			$display(">>Send: %h '%c'", data_byte, data_byte);
			rx = 1'b0;
			#(BIT_PERIOD);
			for (i = 0; i < 8; i = i + 1)
			begin
				rx = data_byte[i];
				#(BIT_PERIOD);
			end
			rx = 1'b1;
			#(BIT_PERIOD);
			#(BIT_PERIOD * 2);
		end
	endtask
	top #(.CLK(CLK_FREQ_HZ), .BAUD_RATE(BAUD_RATE))
		u (.clk(clk), .rx(rx), .rst(rst), .tx(tx), .tx_en(tx_en), .clk_en(clk_en), .led(led), 
		.led_en(led_en));
	always
	begin
		wait (tx == 0);
		#(BIT_PERIOD + (BIT_PERIOD / 2));
		for (j = 0; j < 8; j = j + 1)
		begin
			rx_read_val[j] = tx;
			#(BIT_PERIOD);
		end
		$display("recv: %h '%c'", rx_read_val, rx_read_val);
		#(BIT_PERIOD / 3);
	end
	initial
	begin
		$dumpfile("test_tb.vcd");
		$dumpvars(0, test_tb);
		$display("BIT_PERIOD: %d", BIT_PERIOD);
		clk = 0;
		rst = 1;
	#140;
		rst = 0;
	#400;
		send_serial_byte(97);
	#400;
		send_serial_byte(98);
	#400;
		send_serial_byte(99);
	#400;
		send_serial_byte(100);
	#400;
		send_serial_byte(101);
	#400;
		send_serial_byte(102);
	#12_000;
		$finish;
	end
	always
		#(CLK_PER / 2)
			clk = ~clk;
endmodule

以上。