概要
中古ノート買ってみた。
wsl1のubuntu22.04にBSCをインストールした。
bscでverilogにコンパイル、iverilogで実行してみた。
練習問題、やってみた。
練習問題
sortせよ。
サンプルコード
package Tb;
import StmtFSM::*;
import Vector::*;
(* synthesize *)
module mkTb (Empty);
Vector#(11, Reg#(int)) numbers <- replicateM(mkReg(0));
int vals[11] = {45, 60, 23, 22, 0, 38, 47, 3, 23, 39, 99};
Reg#(int) swapTmp <- mkReg(0);
Reg#(int) ii <- mkRegU;
Reg#(int) jj <- mkRegU;
Stmt test = seq
action
writeVReg(numbers, arrayToVector(vals));
endaction
while (True)
seq
action
for (Integer i = 0; i < 11; i = i + 1)
$display("a[%0d] = %2d", i, numbers[i]);
endaction
for (ii <= 0; ii < 10; ii <= ii + 1)
for (jj <= ii + 1; jj < 11; jj <= jj + 1)
if (numbers[ii] < numbers[jj])
seq
//$display("a[%0d] = %2d", i, numbers[i]);
action
swapTmp <= numbers[ii];
endaction
action
numbers[ii] <= numbers[jj];
endaction
action
numbers[jj] <= swapTmp;
endaction
endseq
action
for (Integer i = 0; i < 11; i = i + 1)
$display("a[%0d] = %2d", i, numbers[i]);
$finish(0);
endaction
endseq
endseq;
mkAutoFSM ( test );
endmodule
endpackage
実行結果
v$ bsc -verilog sort0.bsv
arning: Unknown position: (S0001)
File name `sort0.bsv' does not match package name `Tb'
Verilog file created: mkTb.v
$ iverilog mkTb.v test.v
$ vvp a.out
a[0] = 45
a[1] = 60
a[2] = 23
a[3] = 22
a[4] = 0
a[5] = 38
a[6] = 47
a[7] = 3
a[8] = 23
a[9] = 39
a[10] = 99
a[0] = 99
a[1] = 60
a[2] = 47
a[3] = 45
a[4] = 39
a[5] = 38
a[6] = 23
a[7] = 23
a[8] = 22
a[9] = 3
a[10] = 0
以上。