#概要
ARM Thumb です。32bitでは、ありません。
MOVS Rd, #<imm> N Z Rd := imm imm range 0-255.
MOVS Rd, Rm N Z Rd := Rm Synonym of LSLS Rd, Rm, #0
MOV Rd, Rm Rd := Rm Not Lo to Lo.
MOV Rd, Rm Rd := Rm Any register to any register.
ADDS Rd, Rn, #<imm> N Z C V Rd := Rn + imm imm range 0-7.
ADDS Rd, Rn, Rm N Z C V Rd := Rn + Rm
ADD Rd, Rd, Rm Rd := Rd + Rm Not Lo to Lo.
ADD Rd, Rd, Rm Rd := Rd + Rm Any register to any register.
ADDS Rd, Rd, #<imm> N Z C V Rd := Rd + imm imm range 0-255.
ADCS Rd, Rd, Rm N Z C V Rd := Rd + Rm + C-bit
ADD SP, SP, #<imm> SP := SP + imm imm range 0-508 (word-aligned).
ADD Rd, SP, #<imm> Rd := SP + imm imm range 0-1020 (word-aligned).
ADR Rd, <label> Rd := label label range PC to PC+1020 (word-aligned).
SUBS Rd, Rn, Rm N Z C V Rd := Rn – Rm
SUBS Rd, Rn, #<imm> N Z C V Rd := Rn – imm imm range 0-7.
SUBS Rd, Rd, #<imm> N Z C V Rd := Rd – imm imm range 0-255.
SBCS Rd, Rd, Rm N Z C V Rd := Rd – Rm – NOT C-bit
SUB SP, SP, #<imm> SP := SP – imm imm range 0-508 (word-aligned).
RSBS Rd, Rn, #0 N Z C V Rd := – Rn Synonym: NEGS Rd, Rn
MULS Rd, Rm, Rd N Z * * Rd := Rm * Rd * C and V flags unpredictable in §4T,
CMP Rn, Rm N Z C V update APSR flags on Rn – Rm Can be Lo to Lo, Lo to Hi, Hi to Lo, or Hi to Hi.
CMN Rn, Rm N Z C V update APSR flags on Rn + Rm
CMP Rn, #<imm> N Z C V update APSR flags on Rn – imm imm range 0-255.
ANDS Rd, Rd, Rm N Z Rd := Rd AND Rm
EORS Rd, Rd, Rm N Z Rd := Rd EOR Rm
ORRS Rd, Rd, Rm N Z Rd := Rd OR Rm
BICS Rd, Rd, Rm N Z Rd := Rd AND NOT Rm
MVNS Rd, Rd, Rm N Z Rd := NOT Rm
TST Rn, Rm N Z update APSR flags on Rn AND Rm
LSLS Rd, Rm, #<shift> N Z C* Rd := Rm << shift Allowed shifts 0-31. * C flag unaffected if shift is 0.
LSLS Rd, Rd, Rs N Z C* Rd := Rd << Rs[7:0] * C flag unaffected if Rs[7:0] is 0.
LSRS Rd, Rm, #<shift> N Z C Rd := Rm >> shift Allowed shifts 1-32.
LSRS Rd, Rd, Rs N Z C* Rd := Rd >> Rs[7:0] * C flag unaffected if Rs[7:0] is 0.
ASRS Rd, Rm, #<shift> N Z C Rd := Rm ASR shift Allowed shifts 1-32.
ASRS Rd, Rd, Rs N Z C* Rd := Rd ASR Rs[7:0] * C flag unaffected if Rs[7:0] is 0.
RORS Rd, Rd, Rs N Z C* Rd := Rd ROR Rs[7:0] * C flag unaffected if Rs[7:0] is 0.
LDR Rd, [Rn, #<imm>] Rd := [Rn + imm] imm range 0-124, multiple of 4.
LDRH Rd, [Rn, #<imm>] Rd := ZeroExtend([Rn + imm][15:0]) Clears bits 31:16. imm range 0-62, even.
LDRB Rd, [Rn, #<imm>] Rd := ZeroExtend([Rn + imm][7:0]) Clears bits 31:8. imm range 0-31.
LDR Rd, [Rn, Rm] Rd := [Rn + Rm]
LDRH Rd, [Rn, Rm] Rd := ZeroExtend([Rn + Rm][15:0]) Clears bits 31:16
LDRSH Rd, [Rn, Rm] Rd := SignExtend([Rn + Rm][15:0]) Sets bits 31:16 to bit 15
LDRB Rd, [Rn, Rm] Rd := ZeroExtend([Rn + Rm][7:0]) Clears bits 31:8
LDRSB Rd, [Rn, Rm] Rd := SignExtend([Rn + Rm][7:0]) Sets bits 31:8 to bit 7
LDR Rd, <label> Rd := [label] label range PC to PC+1020 (word-aligned).
LDR Rd, [SP, #<imm>] Rd := [SP + imm] imm range 0-1020, multiple of 4.
LDM Rn!, <loreglist> Loads list of registers (not including Rn) Always updates base register, Increment After.
LDM Rn, <loreglist> Loads list of registers (including Rn) Never updates base register, Increment After.
STR Rd, [Rn, #<imm>] [Rn + imm] := Rd imm range 0-124, multiple of 4.
STRH Rd, [Rn, #<imm>] [Rn + imm][15:0] := Rd[15:0] Ignores Rd[31:16]. imm range 0-62, even.
STRB Rd, [Rn, #<imm>] [Rn + imm][7:0] := Rd[7:0] Ignores Rd[31:8]. imm range 0-31.
STR Rd, [Rn, Rm] [Rn + Rm] := Rd
STRH Rd, [Rn, Rm] [Rn + Rm][15:0] := Rd[15:0] Ignores Rd[31:16]
STRB Rd, [Rn, Rm] [Rn + Rm][7:0] := Rd[7:0] Ignores Rd[31:8]
STR Rd, [SP, #<imm>] [SP + imm] := Rd imm range 0-1020, multiple of 4.
STM Rn!, <loreglist> Stores list of registers Always updates base register, Increment After.
PUSH <loreglist> Push registers onto full descending stack
PUSH <loreglist+LR> Push LR and registers onto full descending stack
POP <loreglist> Pop registers from full descending stack
POP <loreglist+PC> Pop registers, branch to address loaded to PC
POP <loreglist+PC> Pop, branch, and change to ARM state if address[0] = 0
IT{pattern} {cond} Makes up to four following instructions conditional,
B{cond} <label> If {cond} then PC := label label must be within – 252 to + 258 bytes of current instruction.
B <label> PC := label label must be within ±2KB of current instruction.
BL <label> LR := address of next instruction, PC := label This is a 32-bit instruction.
BX Rm PC := Rm AND 0xFFFFFFFE Change to ARM state if Rm[0] = 0.
BLX <label> LR := address of next instruction, PC := label
BLX Rm LR := address of next instruction, PC := Rm AND 0xFFFFFFFE
SXTH Rd, Rm Rd[31:0] := SignExtend(Rm[15:0])
SXTB Rd, Rm Rd[31:0] := SignExtend(Rm[7:0])
UXTH Rd, Rm Rd[31:0] := ZeroExtend(Rm[15:0])
UXTB Rd, Rm Rd[31:0] := ZeroExtend(Rm[7:0])
REV Rd, Rm Rd[31:24] := Rm[7:0], Rd[23:16] := Rm[15:8], Rd[15:8] := Rm[23:16], Rd[7:0] := Rm[31:24]
REV16 Rd, Rm Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:24] := Rm[23:16], Rd[23:16] := Rm[31:24]
REVSH Rd, Rm Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:16] := Rm[7] * &FFFF
SVC <immed_8> Supervisor Call processor exception 8-bit immediate value encoded in instruction. Formerly SWI.
CPSID <iflags> Disable specified interrupts
CPSIE <iflags> Enable specified interrupts
SETEND <endianness> Sets endianness for loads and saves. <endianness> can be BE (Big Endian) or LE (Little Endian).
BKPT <immed_8> Prefetch abort or enter debug state 8-bit immediate value encoded in instruction.
NOP None, might not even consume any time. Real NOP available in ARM v6K and above.
SEV Signal event in multiprocessor system. Executes as NOP in Thumb-2.
WFE Wait for event, IRQ, FIQ, Imprecise abort, or Debug entry request. Executes as NOP in Thumb-2.
WFI Wait for IRQ, FIQ, Imprecise abort, or Debug entry request. Executes as NOP in Thumb-2.
YIELD Yield control to alternative thread.