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高位合成言語アセンブラを作る。

Posted at

#概要

高位合成言語アセンブラを作る。
ソースとアウトプットを載せる。

#閃き

真理値表から、論理回路を作る。

#ソース

make 4
in 0 1
out 2 3
xor 0 1 2
or 0 1 3

#アウトプット verilog

module x(input a, input b, output c, output d);
	assign c = a ^ b;
	assign d = a & b;
endmodule

module testbench;
	reg a,
		b;
	x u(.a(a), .b(b), .c(c), .d(d));
	initial
	begin
		$display("a b c d");
		$monitor("%b %b %b %b", a, b, c, d);
		a = 0; b = 0; #10;
		a = 0; b = 1; #10;
		a = 1; b = 0; #10;
		a = 1; b = 1; #10;
		$finish;
	end
endmodule


以上。

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