Zybo > Chronicles blog 21 > PS / PL interconnected > theoretical bandwidths (DMA使用時) > AXI GPIO / AXI HP / AXI ACP

MicroZed Chronicles リスト http://adiuvoengineering.com/?page_id=285
@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-One-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/418935

Interface	Width	IF Clock	Read BW	Write BW	Combined	No Ports	Total BW
AXI GPIO	32	150 MHz	600 MBps	600 MBps	1200 MBps	2	2400 MBps
AXI HP	64	150 MHz	1200 MBps	1200 MBps	2400 MBps	4	9600 MBps
AXI ACP	64	150 MHz	1200 MBps	1200 MBps	2400 MBps	1	2400 MBps

You must use the Zynq SoC’s DMA controller to achieve the maximum speeds listed in the table above.

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Without using the DMA controller, the maximum transfer rate from the PS to the PL side is 25Mbytes/sec.