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[Verilog超絶初心者]$monitorの罠

Last updated at Posted at 2015-12-27

Icarus Verilogを使っています。

$monitorに、複数bit幅の信号のうち特定bitだけを入力しても変化を検出してくれないようです。

reg a, b;
reg[1:0] c;

initial begin
    c = 0;

    【うまくいかない例】
    $monitor ("%t: c[0] = %b, c[1] = %b", $time, c[0], c[1]);


    #10 c = c+1; 
    #10 c = c+1; 


    【うまくいく例】
    $monitor ("%t: a = %b,  b = %b", $time, a, b);

             a <= c[0]; b <= c[1];
    #10 c = c+1; a <= c[0]; b <= c[1];
    #10 c = c+1; a <= c[0]; b <= c[1];
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