[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 250.000 MHz (CLKIN1_PERIOD, net FCLK_CLK0) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y0 (cell video_sys_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (20.000000), multiplication factor CLKFBOUT_MULT_F (5.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

[DRC AVAL-46] v7v8_mmcm_fvco_rule1: The current computed target frequency, FVCO, is out of range for cell video_sys_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator. The computed FVCO is 371.250 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 5.000, CLKIN1_PERIOD = 13.46801, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
This violation may be corrected by:
  1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run.  Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
  2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
  3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.
  4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.

[BD 41-703] Peripheral </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> is mapped into master segment </processing_system7_0/Data/SEG_processing_system7_0_HP0_DDR_LOWOCM>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "sleep.h"
#include "xparameters.h"
#include "xil_cache.h"
#include "common.h"
#include "videoOut.h"

#define IMAGE_WIDTH  1280
#define IMAGE_HEIGHT 720
#define IMAGE_STRIDE (IMAGE_WIDTH * 3)
//#define IMAGE_STRIDE 0x1000
#define IMAGE_BUFFER_A  0x08000000
#define IMAGE_BUFFER_B  0x09000000

void createTestDrawBuffers()
{
    // todo: Pixel format seems GBR, for some reasons...
    Xil_DCacheDisable();
    /* Create buffer A as solid RED color image */
    for (int v = 0; v < IMAGE_HEIGHT; v++) {
        volatile uint8_t *ptr = (volatile uint8_t*)(IMAGE_BUFFER_A + (IMAGE_STRIDE * v));
        for (int h = 0; h < IMAGE_WIDTH; h++) {
            *ptr++ = 0xFF;  *ptr++ = 0x00; *ptr++ = 0x00;
        }
    }
    /* Create buffer B as color bar */
    for (int v = 0; v < IMAGE_HEIGHT / 2; v++) {
        volatile uint8_t *ptr = (volatile uint8_t*)(IMAGE_BUFFER_B + (IMAGE_STRIDE * v));
        for (int h = 0 * IMAGE_WIDTH / 3; h < 1 * IMAGE_WIDTH / 3; h++) { *ptr++ = 0xFF;  *ptr++ = 0x00; *ptr++ = 0x00; }
        for (int h = 1 * IMAGE_WIDTH / 3; h < 2 * IMAGE_WIDTH / 3; h++) { *ptr++ = 0x00;  *ptr++ = 0xFF; *ptr++ = 0x00; }
        for (int h = 2 * IMAGE_WIDTH / 3; h < 3 * IMAGE_WIDTH / 3; h++) { *ptr++ = 0x00;  *ptr++ = 0x00; *ptr++ = 0xFF; }
    }
    for (int v = IMAGE_HEIGHT / 2; v < IMAGE_HEIGHT; v++) {
        volatile uint8_t *ptr = (volatile uint8_t*)(IMAGE_BUFFER_B + (IMAGE_STRIDE * v));
        for (int h = 0 * IMAGE_WIDTH / 3; h < 1 * IMAGE_WIDTH / 3; h++) { *ptr++ = 0xFF;  *ptr++ = 0xFF; *ptr++ = 0xFF; }
        for (int h = 1 * IMAGE_WIDTH / 3; h < 2 * IMAGE_WIDTH / 3; h++) { *ptr++ = 0x88;  *ptr++ = 0x88; *ptr++ = 0x88; }
        for (int h = 2 * IMAGE_WIDTH / 3; h < 3 * IMAGE_WIDTH / 3; h++) { *ptr++ = 0x00;  *ptr++ = 0x00; *ptr++ = 0x00; }
    }
    Xil_DCacheEnable();
}

int main()
{
    init_platform();
    LOG("Hello World\n\r");

    createTestDrawBuffers();

    /* Initialize HDMI OUT */
    videoOut_init(XPAR_AXIVDMA_0_DEVICE_ID, XPAR_VTC_0_DEVICE_ID, IMAGE_WIDTH, IMAGE_HEIGHT, 3, IMAGE_STRIDE);
    videoOut_setSrcAddress(IMAGE_BUFFER_A);
    videoOut_start();

    /* control to switch buffer */
    while(1) {
        char c = getchar();
        switch (c) {
        case 'a':
            videoOut_stop();
            videoOut_setSrcAddress(IMAGE_BUFFER_A);
            videoOut_start();
            break;
        case 'b':
            videoOut_stop();
            videoOut_setSrcAddress(IMAGE_BUFFER_B);
            videoOut_start();
            break;
        default:
            LOG("none\n");
        }
    }

    cleanup_platform();
    return 0;
}

#ifndef SRC_COMMON_H_
#define SRC_COMMON_H_

#include <stdint.h>

/* common return code */
#define RET_OK       0x00000000
#define RET_NO_DATA  0x00000001
#define RET_TIMEOUT  0x00000002
#define RET_ERR      0x80000001
#define RET_ERR_XDRV 0x80000002 // Error related to Xilinx Driver

/* LOG macros */
#define LOG(str, ...)   {xil_printf("\x1b[39m"); xil_printf("[%s:%d] " str, __FILE__, __LINE__, ##__VA_ARGS__);}
#define LOG_W(str, ...) {xil_printf("\x1b[33m"); xil_printf("[WARNING %s:%d] " str, __FILE__, __LINE__, ##__VA_ARGS__);}
#define LOG_E(str, ...) {xil_printf("\x1b[31m"); xil_printf("[ERROR %s:%d] " str, __FILE__, __LINE__, ##__VA_ARGS__);}

#endif /* SRC_COMMON_H_ */

#ifndef SRC_VIDEOOUT_H_
#define SRC_VIDEOOUT_H_

int videoOut_init(uint16_t vtcDeviceId, uint16_t vdmaDeviceId, int width, int height, int bytePerPixel, int stride);
int videoOut_setSrcAddress(uint32_t address);
int videoOut_start();
void videoOut_stop();

#endif /* SRC_VIDEOOUT_H_ */

#include "common.h"
#include "xparameters.h"
#include "xvtc.h"
#include "xaxivdma.h"
#include "videoOut.h"

static XVtc s_vtc;
static XAxiVdma s_axiVdma;

int videoOut_init(uint16_t vtcDeviceId, uint16_t vdmaDeviceId, int width, int height, int bytePerPixel, int stride)
{
    int status;
    XVtc_Config *configVtc;
    XAxiVdma_Config *configVdma;

    /*** Initialize VTC ***/
    configVtc = XVtc_LookupConfig(vtcDeviceId);
    if (!configVtc){
        LOG_E("XVtc_LookupConfig: %d\n", vtcDeviceId);
        return RET_ERR_XDRV;
    }
    status = XVtc_CfgInitialize(&s_vtc, configVtc, configVtc->BaseAddress);
    if (status != (XST_SUCCESS)) {
        LOG_E("XVtc_CfgInitialize: %d\n", status);
        return RET_ERR_XDRV;
    }


    /*** Initialize VDMA ***/
    configVdma = XAxiVdma_LookupConfig(vdmaDeviceId);
    if (!configVdma){
        LOG_E("XAxiVdma_LookupConfig: %d\n", vdmaDeviceId);
        return RET_ERR_XDRV;
    }

    status = XAxiVdma_CfgInitialize(&s_axiVdma, configVdma, configVdma->BaseAddress);
    if (status != XST_SUCCESS) {
        LOG_E("XAxiVdma_CfgInitialize: %d\n", status);
        return RET_ERR_XDRV;
    }

    XAxiVdma_DmaSetup ReadCfg;
    ReadCfg.VertSizeInput = height;
    ReadCfg.HoriSizeInput = width * bytePerPixel;
    ReadCfg.Stride = stride;
    ReadCfg.FrameDelay = 1;     /* 0 or 1 */
    ReadCfg.EnableCircularBuf = 1;
    ReadCfg.EnableSync = 1;  /* Gen-Lock */
    ReadCfg.PointNum = 0;
    ReadCfg.EnableFrameCounter = 0; /* Endless transfers */
    ReadCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */
    status = XAxiVdma_DmaConfig(&s_axiVdma, XAXIVDMA_READ, &ReadCfg);
    if (status != XST_SUCCESS) {
        LOG_E("XAxiVdma_DmaConfig: %d\n", status);
        return RET_ERR_XDRV;
    }
}

int videoOut_setSrcAddress(uint32_t address)
{
    UINTPTR FrameStoreStartAddr[1];
    FrameStoreStartAddr[0] = address;
    int status = XAxiVdma_DmaSetBufferAddr(&s_axiVdma, XAXIVDMA_READ, FrameStoreStartAddr);
    if (status != XST_SUCCESS) {
        LOG_E("XAxiVdma_DmaSetBufferAddr: %d\n", status);
        return RET_ERR_XDRV;
    }
}

int videoOut_start()
{
    XVtc_Enable(&s_vtc);

    /* Start the Read channel of VDMA */
    int status = XAxiVdma_DmaStart(&s_axiVdma, XAXIVDMA_READ);
    if (status != XST_SUCCESS) {
        LOG_E("XAxiVdma_DmaStart: %d\n", status);
        return RET_ERR_XDRV;
    }
}

void videoOut_stop()
{
    XAxiVdma_DmaStop(&s_axiVdma, XAXIVDMA_READ);
    XVtc_Disable(&s_vtc);
}


void videoOut_dumpStatus()
{
    XAxiVdma_DmaRegisterDump(&s_axiVdma, XAXIVDMA_READ);
}