Structure
PMOS transistor (pull-up)
NMOS transistor (pull-down)
Load capacitance C_L at the output node
When the input V_in transitions from 0 → 1, the PMOS turns off and the NMOS turns on. The output node discharges toward 0 V.
When the input transitions from 1 → 0, the PMOS turns on and the NMOS turns off. The output node charges toward V_DD.
Delay Model
Since the output node has capacitive loading C_L, the transient response can be approximated by an RC exponential.
Discharge (High → Low transition):
V_out(t) = V_DD * exp(-t / (R_n C_L))
where R_n is the equivalent resistance of the NMOS.
Charge (Low → High transition):
V_out(t) = V_DD * (1 - exp(-t / (R_p C_L)))
where R_p is the equivalent resistance of the PMOS.
Propagation Delay
If the switching threshold is set at V_DD / 2:
High → Low transition:
t_pHL = R_n C_L ln(2) ≈ 0.693 R_n C_L
Low → High transition:
t_pLH = R_p C_L ln(2) ≈ 0.693 R_p C_L
Average Propagation Delay
The propagation delay of the inverter is usually defined as the average of the two transition times:
t_pd = (t_pHL + t_pLH) / 2
= (0.693 C_L (R_n + R_p)) / 2
Summary
• A CMOS inverter can be modeled as a resistive element driving a capacitive load.
• The output follows an exponential charging/discharging behavior.
• The propagation delay is approximately 0.7 RC.