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@p3000

SystemVerilog 2017

Posted at

System Verilogの改版

IEEEのページをみると
IEEE Approved Draft Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
STANDARD by IEEE, 03/15/2018
とかいてあります。

DraftがApproveされ、STANDARD by IEEE, 03/15/2018とあるので来年の3月に正式に発行されるということですかね？

今までのIEEE 1800-2012の方は
Superseded by: 1800-2017
となっているので新規格はIEEE 1800-2017となりこちらがActive standardになっています。

SVAの部分はどう変わったのでしょうか？

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