windowsでiverilog その157

概要　

windowsでiverilogやってみた。
RP2040な、verilog見つけたので、テストベンチ書いてみた。

投入したpioasm

.program spi
.side_set 1
    out pins 1 side 0 [1]
    in  pins 1 side 1 [1]

サンプルコード

`timescale 1ns/100ps
module test();
	localparam NONE = 0;
	localparam INSTR = 1;
	localparam PEND = 2;
	localparam PULL = 3;
	localparam PUSH = 4;
	localparam GRPS = 5;
	localparam EN = 6;
	localparam DIV = 7;
	localparam SIDES = 8;
	localparam IMM = 9;
	localparam SHIFT = 10;
	reg clk;
	reg reset;
	reg [31:0] din;
	reg [4:0] index;
	reg [3:0] action;
	reg [1:0] mindex;
	reg [31:0] gpio_in = 0;
	reg [15:0] program [0:31];
	wire [31:0] gpio_out;
	wire [31:0] gpio_dir;
	wire [31:0] dout;
	wire [3:0] tx_full;
	wire [3:0] rx_empty;
	wire [5:0] plen = 2;
	wire [23:0] div = 24'h0C80;
	wire [31:0] pin_grps = 32'h20100001;
	wire [31:0] exec_ctrl = 32'h00001000;
	integer i;
	task act (input [3:0] a, input [31:0] d);
		begin
			@(negedge clk);
			action = a;
			din = d;
			@(posedge clk);
		end
	endtask
	pio pio_1 (.clk(clk), .reset(reset), .action(action), .index(index), .mindex(mindex), .din(din), .dout(dout), .gpio_in(gpio_in), .gpio_out(gpio_out), .gpio_dir(gpio_dir), .tx_full(tx_full), .rx_empty(rx_empty));
	initial
		$readmemh("spi.mem", program);
	initial
	begin
		clk = 1'b0;
	end
	always
	begin
		#20
			clk = !clk;
	end
	initial
	begin
		reset = 1'b1;
		repeat(2) @(posedge clk);
		reset = 1'b0;
		for (i = 0; i < plen; i++)
		begin
			index = i;
			act(INSTR, program[i]);
		end
		mindex = 0;
		act(PEND, exec_ctrl);
		act(DIV, div);
		act(GRPS, pin_grps);
		act(SHIFT, 32'h10830000);
		act(EN, 1);
		act(NONE, 0);
		repeat(2) @(posedge clk);
		gpio_in[0] = 1;
		for (i = 1; i < 3; i++)
		begin
			act(PUSH, i << 30);
			action = 0;
			repeat(500) @(posedge clk);
			act(PULL, 0);
			action = 0;
		end
		$finish;
	end
	initial
	begin
		$dumpfile("test.vcd");
		$dumpvars(0, test);
		$display(" ac    din     out ");
		$monitor(" %h    %h      %h ", action, din, gpio_out);
	end
endmodule

実行結果

>vvp a.out
WARNING: pio3.v:870: $readmemh(spi.mem): Not enough words in the file for the requested range [0:31].
VCD info: dumpfile test.vcd opened for output.
 ac    din     out
 x    xxxxxxxx      xxxxxxxx
 x    xxxxxxxx      00000000
 1    00006101      00000000
 1    00005101      00000000
 2    00001000      00000000
 7    00000c80      00000000
 5    20100001      00000000
 a    10830000      00000000
 6    00000001      00000000
 0    00000000      00000000
 4    40000000      00000000
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000002
 0    40000000      00000003
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000000
 0    40000000      00000001
 0    40000000      00000000
 3    00000000      00000000
 0    00000000      00000000
 4    80000000      00000000
 0    80000000      00000000
 0    80000000      00000002
 0    80000000      00000003
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 0    80000000      00000001
 0    80000000      00000000
 3    00000000      00000000
pio3.v:907: $finish called at 406200 (100ps)
 0    00000000      00000000

以上。