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windowsでiverilog その36

概要

windowsでiverilogやってみた。
oneshot書いてみる。

写真

image

サンプルコード


module oneshot(input clk, input rst, input in, output reg out);
    reg prev = 0;
    always @(posedge clk)
    begin
        if (in ^ prev)
            out <= in;
        else
            out <= 0;
        prev <= in;
    end
endmodule

module test;
    reg clk,
        in;
    oneshot u(.clk(clk), .in(in), .out(out));
    initial
    begin
        clk = 0;
        in = 0;
        #2
            in = 1;
        #6
            in = 0;
        #2
            in = 1;
        #6
            in = 0;
        #20
            $finish;
    end
    always
    begin
        #1
            clk = ~clk;
    end
    initial
    begin
        $dumpfile("test.vcd");
        $dumpvars(0, u);
    end
endmodule




以上。

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