windowsでiverilog その107

概要　

windowsでiverilogやってみた。
シリパラ変換、書いてみた。

サンプルコード

module seripara8(input sck, input rst, input en, input sda, output reg [7:0] q);
	always @(posedge sck)
	begin
		if (rst)
			q <= 8'h0;
		else if (en)
		begin
			q <= { q[6:0], sda };
		end
	end
endmodule


module test;
	reg sck;
	reg rst;
	reg en;
	reg sda;
	wire [7:0] q;
	seripara8 u(.sck(sck), .rst(rst), .en(en), .sda(sda), .q(q));
	initial
	begin
		sck = 0;
		rst = 1;
		en = 0;
		sda = 0;
		$display("sck, rst, en, sda, q");
		$monitor("%b %b %b %b %b", sck, rst, en, sda, q);
		#2
			rst = 0;
			en = 1;
			sck = 1;
			sda = 1;
		#2
			sck = 0;
			sda = 0;
		#2
			sck = 1;
		#2
			sck = 0;
		#2
			sck = 1;
		#2
			sck = 0;
		#2
			sck = 1;
		#2
			sck = 0;
		#2
			sck = 1;
		#2
			sck = 0;
		#2
			sck = 1;
		#2
			sck = 0;
		#2
			sck = 1;
		#2
			sck = 0;
		#2
			sck = 0;
			en = 0;
		#2
			$finish;
	end
endmodule

結果

sck, rst, en, sda, q
0 1 0 0 xxxxxxxx
1 0 1 1 xxxxxxx1
0 0 1 0 xxxxxxx1
1 0 1 0 xxxxxx10
0 0 1 0 xxxxxx10
1 0 1 0 xxxxx100
0 0 1 0 xxxxx100
1 0 1 0 xxxx1000
0 0 1 0 xxxx1000
1 0 1 0 xxx10000
0 0 1 0 xxx10000
1 0 1 0 xx100000
0 0 1 0 xx100000
1 0 1 0 x1000000
0 0 1 0 x1000000
0 0 0 0 x1000000

以上。