概要
インタープリタを作ってみた。
avrインタープリター書いてみた。
avrの命令調べてみた。
命令セット
| Command | Operands | Operation | Description | Flags | Cycles | Opcode |
|---|---|---|---|---|---|---|
| ADC | Rd, Rr | Rd←Rd + Rr + C | Add two registers with carry | --HSVNZC | 1 | 0001 11rd dddd rrrr |
| ADD | Rd,Rr | Rd←Rd + Rr | Add two registers | --HSVNZC | 1 | 0000 11rd dddd rrrr |
| ADIW | Rh:Rl, K | Rh:Rl←Rh:Rl + K | Add immediate to Word (0 ≤ K ≤ 63) | ---SVNZC | 2 | 1001 0110 KKdd KKKK |
| AND | Rd,Rr | Rd←Rd • Rr | Logical AND two registers | ---SVNZ-, V cleared | 1 | 0010 00rd dddd rrrr |
| ANDI | Rd, K | Rd←Rd • K | Logical AND with immediate (16 ≤ d ≤ 31) | ---SVNZ-, V cleared | 1 | 0111 KKKK dddd KKKK |
| ASR | Rd | C←Rd(0), Rd(6…0) ←Rd(7…1), Rd(7) ←Rd(7) | Arithmetic shift right | ---SVNZC | 1 | 1001 010d dddd 0101 |
| BCLR | s | SREG(s) ←0 | Clear bit in status register | SREG(s) | 1 | 1001 0100 1sss 1000 |
| BLD | Rd,b | Rd(b) ←T | Load bit in register from T | -T------ | 1 | 1111 100d dddd 0bbb |
| BRBC | s,k | if(SREG(s) = 0) PC←PC + k + 1 | Branch if status register flag cleared | -------- | 1,2* | 1111 01kk kkkk ksss |
| BRBS | s,k | if(SREG(s) = 1) PC←PC + k + 1 | Branch if status register flag set | -------- | 1,2* | 1111 00kk kkkk ksss |
| BRCC | k | if(C=0) then PC←PC + k + 1 | Branch if carry cleared, Same as brbc 0,k and brsh | -------- | 1,2* | 1111 01kk kkkk k000 |
| BRCS | k | if(C=1) then PC←PC + k + 1 | Branch if carry set, Same as brbs 0,k and brlo | -------- | 1,2* | 1111 00kk kkkk k000 |
| BREAK | For on-chip debug only | -------- | 1 | 1001 0101 1001 1000 | ||
| BREQ | k | if(Z=1) then PC←PC + k + 1 | Branch if equal, Same as brbs 1,k | -------- | 1,2* | 1111 00kk kkkk k001 |
| BRGE | k | if(S=0) then PC←PC + k + 1 | Branch if greater or equal (signed), Same as brbc 4,k | -------- | 1,2* | 1111 01kk kkkk k100 |
| BRHC | k | if(H=0) then PC←PC + k + 1 | Branch if half-carry flag cleared, Same as brbc 5,k | -------- | 1,2* | 1111 01kk kkkk k101 |
| BRHS | k | if(H=1) then PC←PC + k + 1 | Branch if half-carry flag set, Same as brbs 5,k | -------- | 1,2* | 1111 00kk kkkk k101 |
| BRID | k | if(I=0) then PC←PC + k + 1 | Branch if interrupt disabled, Same as brbc 7,k | -------- | 1,2* | 1111 01kk kkkk k111 |
| BRIE | k | if(I=1) then PC←PC + k + 1 | Branch if interrupts enabled, Same as brbs 7,k | -------- | 1,2* | 1111 00kk kkkk k111 |
| BRLO | k | if(C=1) then PC←PC + k + 1 | Branch if lower, unsigned, Same as brbs 0,k and brcs | -------- | 1,2* | 1111 00kk kkkk k000 |
| BRLT | k | if(S=1) then PC←PC + k + 1 | Branch if less than (signed), Same as brbs 4,k | -------- | 1,2* | 1111 00kk kkkk k100 |
| BRMI | k | if(N=1) then PC←PC + k + 1 | Branch if minus, Same as brbs 2,k | -------- | 1,2* | 1111 00kk kkkk k010 |
| BRNE | k | if(Z=0) then PC←PC + k + 1 | Branch if not equal, Same as brbc 1,k | -------- | 1,2* | 1111 01kk kkkk k001 |
| BRPL | k | if(N=0) then PC←PC + k + 1 | Branch if plus, Same as brbc 2,k | -------- | 1,2* | 1111 01kk kkkk k010 |
| BRSH | k | if(C=0) then PC←PC + k + 1 | Branch if same or higher, unsigned, Same as brbc 0,k and brcc | -------- | 1,2* | 1111 01kk kkkk k000 |
| BRTC | k | if(T=0) then PC←PC + k + 1 | Branch if T flag cleared, Same as brbc 6,k | -------- | 1,2* | 1111 01kk kkkk k110 |
| BRTS | k | if(T=1) then PC←PC + k + 1 | Branch if T flag set, Same as brbs 6,k | -------- | 1,2* | 1111 00kk kkkk k110 |
| BRVC | k | if(V=0) then PC←PC + k + 1 | Branch if overflow flag is cleared, Same as brbc 3,k | -------- | 1,2* | 1111 01kk kkkk k011 |
| BRVS | k | if(V=1) then PC←PC + k + 1 | Branch if overflow flag is set, Same as brbs 3,k | -------- | 1,2* | 1111 00kk kkkk k011 |
| BSET | s | SREG(s) ←1 | Set bit in status register | SREG(s) | 1 | 1001 0100 0sss 1000 |
| BST | Rr,b | T←Rr(b) | Bit store from register to T | -T------ | 1 | 1111 101d dddd 0bbb |
| CALL | k | PC←k; Stack←PC + 2; SP←SP–2 | Direct subroutine call. 0≤k≤64K | -------- | 4 | 1001 010k kkkk 111k kkkk kkkk kkkk kkkk |
| CBI | P, b | IOP ←0 | Clear bit in I/O register, only for 0≤P≤31 | -------- | 2 | 1001 1000 PPPP Pbbb |
| CBR | Rd, K | Rd←Rd•K | Clear bit(s) in register, only for 16≤d≤31 | ---SVNZ-, V cleared | 1 | As per ANDi with K Complemented |
| CLC | C←0 | Clear carry flag, Same as bclr 0 | -------C | 1 | 1001 0100 1000 1000 | |
| CLH | H←0 | Clear half-carry flag, Same as bclr 5 | --H----- | 1 | 1001 0100 1101 1000 | |
| CLI | I←0 | Clear global interrupt flag (disable interrupts), Same as bclr 7 | I------- | 1 | 1001 0100 1111 1000 | |
| CLN | N←0 | Clear negative flag, Same as bclr 2 | -----N-- | 1 | 1001 0100 1010 1000 | |
| CLR | Rd | Rd←Rd ⊕ Rd | Clear register, Same as eor Rd, Rd | ---SVNZ-, Z set; S,V,N cleared | 1 | 0010 01Dd dddd DDDD (DDDDD=ddddd) |
| CLS | S←0 | Clear signed flag, Same as bclr 4 | ---S---- | 1 | 1001 0100 1100 1000 | |
| CLT | T←0 | Clear T flag, Same as bclr 6 | -T------ | 1 | 1001 0100 1110 1000 | |
| CLV | V←0 | Clear overflow flag, Same as bclr 3 | ----V--- | 1 | 1001 0100 1011 1000 | |
| CLZ | Z←0 | Clear zero flag, Same as bclr 1 | ------Z- | 1 | 1001 0100 1001 1000 | |
| COM | Rd | Rd←Rd or Rd←$FF – Rd | One’s complement (inversion) | ---SVNZC, V cleared, C set | 1 | 1001 010d dddd 0000 |
| CP | Rd, Rr | Rd – Rr | Compare | --HSVNZC | 1 | 0001 01rd dddd rrrr |
| CPC | Rd,Rr | Rd – Rr – C | Compare with Carry | --HSVNZC | 1 | 0000 01rd dddd rrrr |
| CPI | Rd, K | Rd – K | Compare with immediate, 16≤ d ≤ 31 | --HSVNZC | 1 | 0011 KKKK dddd KKKK |
| CPSE | Rd,Rr | if(Rd=Rr) PC←PC + 2 (or 3) | Compare, skip if equal. | -------- | 1,2, 3† | 0001 00rd dddd rrrr |
| DEC | Rd | Rd←Rd – 1 | Decrement register | ---SVNZ- | 1 | 1001 010d dddd 1010 |
| EOR | Rd,Rr | Rd←Rd ⊕ Rr | Exclusive OR two registers | ---SVNZ-, V cleared | 1 | 0010 01rd dddd rrrr |
| FMUL | Rd, Rr | R1:R0 ← Rd * Rr | Multiply unsigned 1.7 fractional number by another. 16 ≤ d ≤ 23, 16 ≤ r ≤ 23 | ------ZC | 2 | 0000 0011 0ddd 1rrr |
| FMULS | Rd, Rr | R1:R0 ← Rd * Rr | Multiply signed 1.7 fractional number by another. 16 ≤ d ≤ 23, 16 ≤ r ≤ 23 | ------ZC | 2 | 0000 0011 1ddd 0rrr |
| FMULSU | Rd, Rr | R1:R0 ← Rd * Rr | Multiply 1.7 fractional signed number (Rd) by 1.7 fractional unsigned number (Rr). 16 ≤ d ≤ 23, 16 ≤ r ≤ 23 | ------ZC | 2 | 0000 0011 1ddd 1rrr |
| ICALL | PC←Z; Stack←PC + 1; SP←SP–2 | Indirect call to Z | -------- | 3 | 1001 0101 0000 1001 | |
| IJMP | PC←Z | Indirect Jump to Z | -------- | 2 | 1001 0100 0000 1001 | |
| IN | Rd, P | Rd←IO[P] | Load an I/O Location to Register | -------- | 1 | 1011 0PPd dddd PPPP |
| INC | Rd | Rd←Rd + 1 | Increment register | ---SVNZ- | 1 | 1001 010d dddd 0011 |
| JMP | k | PC ← k | Jump to address anywhere in program memory. (0 ≤ k ≤ 4M) | -------- | 3 | 1001 010k kkkk 110k kkkk kkkk kkkk kkkk |
| LD | Rd, W | Rd←M[W] | Load Indirect (Y or Z case) | -------- | 2 | 1000 000d dddd W000 |
| LD | Rd, X | Rd←M[X] | Load Indirect (X case) | -------- | 2 | 1001 000d dddd 1100 |
| LDD | Rd,W+ q | Rd←M[W+q] | Load Indirect with Displacement (Y or Z only) | -------- | 2 | 10q0 qq0d dddd Wqqq |
| LD | Rd, W+ | Rd←M[W]; W←W+1 | Load Indirect with Postincrement (Y or Z) | -------- | 2 | 1001 000d dddd W001 |
| LD | Rd, X+ | Rd←M[X]; X←X+1 | Load Indirect with Postincrement (X) | -------- | 2 | 1001 000d dddd 1101 |
| LD | Rd, -W | W←W-1; Rd←M[W] | Load Indirect with Pre-decrement (Y or Z) | -------- | 2 | 1001 000d dddd W010 |
| LD | Rd, -X | X←X-1; Rd←M[X] | Load Indirect with Pre-decrement (X) | -------- | 2 | 1001 000d dddd 1110 |
| LDI | Rd, K | Rd←K | Load Immediate, 16 ≤ d ≤ 31 | -------- | 1 | 1110 KKKK dddd KKKK |
| LDS | Rd, k | Rd←M[k] | Load Direct from SRAM, 0≤k≤65535 | -------- | 2 | 1001 000d dddd 0000 kkkk kkkk kkkk kkkk |
| LPM | R0←PM[Z] | Load program memory, Z contains a byte address. Least significant bit of Z selects low byte of the program word (if 0) or high byte (if 1) | -------- | 3 | 1001 0101 1100 1000 | |
| LPM | Rd, Z | Rd←PM[Z] | As above, destination is Rd | -------- | 3 | 1001 000d dddd 0100 |
| LPM | Rd, Z+ | R0←PM[Z] Z←Z+1 | As above, destination is Rd. Z is incremented | -------- | 3 | 1001 000d dddd 0100 |
| LSL | Rd | C←Rd(7); Rd(7…1) ←Rd(6…0); Rd(0) ←0 | Logical Shift Left, Same as add Rd,Rd | --HSVNZC | 1 | 0000 11Dd dddd DDDD (DDDDD=ddddd) |
| LSR | Rd | C←Rd(0); Rd(6…0) ←Rd(7…1); Rd(7) ←0 | Logical Shift Right | ---SVNZC, N←0 | 1 | 1001 010d dddd 0110 |
| MOV | Rd, Rr | Rd←Rr | Move between registers | -------- | 1 | 0010 11rd dddd rrrr |
| MOVW | Rd, Rr | Rd+1:Rd← Rr+1:Rr | Copy one register pair to another. d=0,2,4…30; r=0,2,4…30 | -------- | 1 | 0000 0001 dddd rrrr |
| MUL | Rd, Rr | R1:R0 ← Rd * Rr | Multiply two 8-bit unsigned numbers. (Unsigned result) | ------ZC | 2 | 1001 11rd dddd rrrr |
| MULS | Rd, Rr | R1:R0 ← Rd * Rr | Multiply two 8-bit signed numbers. 16 ≤ d ≤ 31, 16 ≤ r ≤ 31 | ------ZC | 2 | 0000 0010 dddd rrrr |
| MULSU | Rd, Rr | R1:R0 ← Rd * Rr | Multiply 8-bit signed number (Rd) by 8-bit unsigned number (Rr). 16 ≤ d ≤ 23, 16 ≤ r ≤ 23 | ------ZC | 2 | 0000 0011 0ddd 0rrr |
| NEG | Rd | Rd←$00 – Rd | Two’s complement (negation) | --HSVNZC | 1 | 1001 010d dddd 0001 |
| NOP | No operation | -------- | 1 | 0000 0000 0000 0000 | ||
| OR | Rd,Rr | Rd←Rd or Rr | Logical OR two registers | ---SVNZ-, V cleared | 1 | 0010 10rd dddd rrrr |
| ORI | Rd, K | Rd←Rd or K | Logical OR with immediate, 16 ≤ d ≤ 31 | ---SVNZ-, V cleared | 1 | 0110 KKKK dddd KKKK |
| OUT | P, Rr | IO[P] ←Rr | Store Register to I/O Location | -------- | 1 | 1011 1PPr rrrr PPPP |
| POP | Rd | SP←SP+1; Rd←STACK | Pop register from stack | -------- | 2 | 1001 000d dddd 1111 |
| PUSH | Rr | STACK←Rr; SP←SP–1 | Push register on Stack | -------- | 2 | 1001 001r rrrr 1111 |
| RCALL | k | PC←PC + k + 1; Stack←PC + 1; SP←SP–2 | Relative Subroutine Call, -2048 ≤ k ≤ 2047 | -------- | 3 | 1101 kkkk kkkk kkkk |
| RET | SP←SP+2; PC←Stack | Subroutine return | -------- | 4 | 1001 0101 0000 1000 | |
| RETI | SP←SP+2; PC←Stack | Return from interrupt (and enable interrupts) | I-------, I is set | 4 | 1001 0101 0001 1000 | |
| RJMP | k | PC←PC + k + 1; | Relative Jump, -2048 <= k <= 2047 | -------- | 2 | 1100 kkkk kkkk kkkk |
| ROL | Rd | C←Rd(7); Rd(7…1) ←Rd(6…0); Rd(0) ←C | Rotate left through carry, Same as adc Rd,Rd | --HSVNZC | 1 | 0001 11Dd dddd DDDD (DDDDD=ddddd) |
| ROR | Rd | C←Rd(0); Rd(6…0) ←Rd(7…1); Rd(7) ←C | Rotate right through carry | ---SVNZC | 1 | 1001 010d dddd 0111 |
| SBC | Rd, Rr | Rd←Rd – Rr – C | Subtract two registers with carry | --HSVNZC | 1 | 0000 10rd dddd rrrr |
| SBCI | Rd, K | Rd←Rd – K – C | Subtract immediate with carry, 16 ≤ d ≤ 31 | --HSVNZC | 1 | 0100 KKKK dddd KKKK |
| SBI | P, b | IOP ←1 | Set bit in I/O register, 0<=P<=31 | -------- | 2 | 1001 1010 PPPP Pbbb |
| SBIC | P, b | if(IOP = 0) PC←PC + 2 (or 3) | Skip if bit in I/O register is cleared, 0<=P<=31 | -------- | 1,2, 3† | 1001 1001 PPPP Pbbb |
| SBIS | P, b | if(IOP = 1) PC←PC + 2 (or 3) | Skip if bit in I/O register is set, 0<=P<=31 | -------- | 1,2, 3† | 1001 1011 PPPP Pbbb |
| SBIW | Rh:Rl, K | Rh:Rl←Rh:Rl–K | Subtract immediate from word, 0 ≤ K ≤ 63 | ---SVNZC | 2 | 1001 0111 KKdd KKKK |
| SBR | Rd, K | Rd←Rd or K | Set bit(s) in register, 16 ≤ d ≤ 31, same as ori | ---SVNZ-, V cleared | 1 | 0110 KKKK dddd KKKK |
| SBRC | Rr, b | if(Rr(b) = 0) PC←PC + 2 (or 3) | Skip if bit in register is cleared | -------- | 1,2, 3† | 1111 110r rrrr 0bbb |
| SBRS | Rr, b | if(Rr(b) = 1) PC←PC + 2 (or 3) | Skip if bit in register is set | -------- | 1,2, 3† | 1111 111r rrrr 0bbb |
| SEC | C←1 | Set carry flag, Same as bset 0 | -------C | 1 | 1001 0100 0000 1000 | |
| SEH | H←1 | Set half-carry flag, Same as bset 5 | --H----- | 1 | 1001 0100 0101 1000 | |
| SEI | I←1 | Set global interrupt flag (enable interrupts). Instruction following sei will always be executed before any pending interrupts are handled. Same as bset 7 | I------- | 1 | 1001 0100 0111 1000 | |
| SEN | N←1 | Set negative flag, Same as bset 2 | -----N-- | 1 | 1001 0100 0010 1000 | |
| SER | Rd | Rd←$FF | Set register, 16 ≤ d ≤ 31, Same as LDI Rd, $FF | -------- | 1 | 1110 1111 dddd 1111 |
| SES | S←1 | Set signed flag, Same as bset 4 | ---S---- | 1 | 1001 0100 0100 1000 | |
| SET | T←1 | Set T flag, Same as bset 6 | -T------ | 1 | 1001 0100 0110 1000 | |
| SEV | V←1 | Set overflow flag, Same as bset 3 | ----V--- | 1 | 1001 0100 0011 1000 | |
| SEZ | Z←1 | Set zero flag, Same as bset 1 | ------Z- | 1 | 1001 0100 0001 1000 | |
| SLEEP | Sleep. Sets CPU in sleep mode defined by the MCU control register | -------- | 1 | 1001 0101 1000 1000 | ||
| SPM | PM[Z] ←R1:R0 | Store program memory – see instruction reference manual for details. | -------- | Varies | 1001 0101 1110 1000 | |
| ST | W, Rr | M[W] ←Rr | Store Indirect (Y or Z cases) | -------- | 2 | 1000 001r rrrr W000 |
| ST | X, Rr | M[X] ←Rr | Store Indirect (X case) | -------- | 2 | 1001 001r rrrr 1100 |
| ST | W+, Rr | M[W] ←Rr; W←W+1 | Store Indirect with Postincrement (Y or Z) | -------- | 2 | 1001 001r rrrr W001 |
| ST | X+, Rr | M[X] ←Rr; X←X+1 | Store Indirect with Postincrement (X) | -------- | 2 | 1001 001r rrrr 1101 |
| ST | -W, Rr | W←W-1; M[W] ←Rr | Store Indirect with Pre-decrement (Y or Z) | -------- | 2 | 1001 001r rrrr W010 |
| ST | -X, Rr | X←X-1; M[X] ←Rr | Store Indirect with Pre-decrement (X) | -------- | 2 | 1001 001r rrrr 1110 |
| STD | W+q,Rr | M[W+q] ←Rr | Store Indirect with Displacement (Y or Z only) | -------- | 2 | 10q0 qq1r rrrr Wqqq |
| STS | k, Rr | M[k] ←Rr | Store Direct To SRAM | -------- | 2 | 1001 001r rrrr 0000 kkkk kkkk kkkk kkkk |
| SUB | Rd, Rr | Rd←Rd - Rr | Subtract two registers | --HSVNZC | 1 | 0001 10rd dddd rrrr |
| SUBI | Rd, K | Rd←Rd – K | Subtract immediate, 16 ≤ d ≤ 31 | --HSVNZC | 1 | 0101 KKKK dddd KKKK |
| SWAP | Rd | Rd(7…4) ←Rd(3…0); Rd(3…0) ←Rd(7…4) | Swap nibbles (i.e. high 4 bits is exchanged with low 4 bits) | -------- | 1 | 1001 010d dddd 0010 |
| TST | Rd | Rd←Rd • Rd | Test for zero or minus, same as And Rd, Rd | ---SVNZ-, V cleared | 1 | 0010 00Dd dddd DDDD (DDDDD=ddddd) |
| WDR | Watchdog reset | -------- | 1 | 1001 0101 1010 1000 |