windowsでiverilog その34

概要

windowsでiverilogやってみた。
負数、書いてみる。

サンプルコード

module mul(input clk, rst, input signed [3:0] a, input signed [3:0] b, output signed [7:0] out);
	reg signed [7:0] out;
	always @(posedge clk or negedge rst)
	begin
		if (!rst)
		begin
			out <= 0;
		end
		else
		begin
			out <= a * b;
		end
	end
endmodule

module test();
	reg clk;
	reg rst;
	reg signed [3:0] a;
	reg signed [3:0] b;
	wire signed [7:0] out;
	mul u(.clk(clk), .rst(rst), .a(a), .b(b), .out(out));
	integer i,
		j;
	initial
	begin
		$monitor("%d %d %d", a, b, out);
		clk = 0;
		rst = 1;
		#10
			rst = 0;
		#10
			rst = 1;
		#10
			a = -5;
			b = -5;
		#10
			$finish;
	end
	always
	begin
		#5
			clk = 1;
		#5
			clk = 0;
	end
endmodule

実行結果

 x  x    x
 x  x    0
 x  x    x
-5 -5    x
-5 -5   25

以上。