概要
blocklyでverilog、書いてみた。
verilogのblockが探せないので、blockを調べてみた。
block一覧
| カテゴリー | 名前 | 表示 | コード |
|---|---|---|---|
| Port Declaration | module_dec | Create new module with name | module |
| Port Declaration | input_block | input | input |
| Port Declaration | output_block | output | output |
| Port Declaration | wire_block | wire | wire |
| Port Declaration | reg_block | reg | reg |
| Port Declaration | inout_block | inout | inout |
| Port Declaration | end_module | end | endmodule |
| Dynamic Variables | VARIABLE | ||
| Gate level1 | and_block | and | and |
| Gate level1 | or_block | or | or |
| Gate level1 | not_gate | not | not |
| Gate level1 | xor_block | xor | xor |
| Gate level2 | nand_block | nand | nand |
| Gate level2 | nor_block | nor | nor |
| Gate level2 | xnor_block | xnor | xnor |
| Behavioral | intial | initial | intial |
| Behavioral | intial_par | initial par | initial fork |
| Behavioral | always_blk | condition | always |
| Behavioral | always_simu | ||
| Behavioral | logic_operation_2 | ||
| Behavioral | variables_set_parallel | ||
| Data Flow | assign_block | assign | assign |
| Conditions | controls_if | if | if |
| Conditions | controls_ifelse | if | if |
| Conditions | if_else_block | if | if |
| Conditions | logic_ternary | ||
| Logic Operators | logic_negate | negate | ! |
| Logic Operators | logic_boolean | boolean | 1or0 |
| Logic Operators | logic_compare | compare | |
| Logic Operators | logic_operation | operation | |
| Logic Operators | logic_null | null | X |
| Bitwise Operators | logic_operation3 | ||
| Bitwise Operators | logic_negate3 | ||
| Bitwise Operators | logic_boolean | ||
| Bitwise Operators | logic_null | ||
| Operators | math_arithmetic | math | +-*/ |
| Operators | text | text | text |
| Operators | bit_select | bit | bit |
| Operators | pos_edge | name | posedge |
| Operators | neg_edge | name | negedge |
| Operators | concat | concat | concat |
| Values | zero | 0 | 0 |
| Values | one | 1 | 1 |
| Values | high_impedence | z | z |
| Values | dont_care | X | X |
| Numbers | math_number | num | num |
| Numbers | decimal_binary | val | 'b |
| Numbers | decimal_hexa | val | 'h |
| Numbers | decimal_octa | val | 'o |
| Numbers | decimal_binary_return | binary | 'b |
| Numbers | decimal_hexa_return | hexa | 'h |
| Numbers | decimal_octal_return | octal | 'o |
| Loops | forever_loop | forever | forever |
| Loops | repeat_loop | repeat | repeat |
| Loops | while_loop | while | while |
| Simulation1 | module_test | test | module |
| Simulation1 | input_simu | input | reg |
| Simulation1 | output_simu | output | wire |
| Simulation1 | end_module | end | endmodule |
| Simulation2 | display_block | display | $display |
| Simulation2 | monitor_block | monitor | $monitor |
| Simulation2 | time_block | time | # |
| Simulation2 | finish_block | finish | $finish |
以上。