windowsでiverilog その29

概要

windowsでiverilogやってみた。
遅いI/Oのためにwait、書いてみる。

サンプルコード

module wait0(input clk, rst, output out, output [2:0] state);
	reg out;
	reg [2:0] state;
	reg [23:0] wait_time;
	always @(posedge clk or negedge rst)
	begin
		if (!rst)
		begin
			out <= 0;
			state <= 0;
		end
		else
		begin
			case (state)
			0:
			begin
				out <= 1;
				state <= 1;
			end
			1:
			begin
				out <= 0;
				wait_time <= 24'd10;
				state <= 5;
			end
			2:
			begin
				out <= 1;
				state <= 3;
			end
			3:
			begin
				out <= 0;
				state <= 4;
			end
			4:
			begin
				out <= 0;
				state <= 0;
			end
			5:
			begin
				wait_time <= wait_time - 1;
				if (wait_time <= 0)
				begin
					state <= 2;
				end
			end
			endcase
		end
	end
endmodule

module test();
	reg clk;
	reg rst;
	wire out;
	wire [2:0] state;
	wait0 u(.clk(clk), .rst(rst), .out(out), .state(state));
	initial
	begin
		$monitor("%b %d", out, state);
		clk = 0;
		rst = 1;
		#10
			rst = 0;
		#10
			rst = 1;
		#200
			$finish;
	end
	always
	begin
		#5
			clk = 1;
		#5
			clk = 0;
	end
endmodule

実行結果

x x
0 0
1 1
0 5
0 2
1 3
0 4
0 0
1 1
0 5

以上。