blocklyでverilog その2

概要

blocklyでverilog、書いてみた。
7セグメント・デコーダー書いてみた。

写真

成果物

生成したverilog

module x(input [3:0] data, output [6:0] code);
	reg [6:0] code;
	wire [3:0] data;
	always @ (data)
	begin
		if (data == 0)
		begin
			code = (7'h7e);
		end
		else
		begin
			if (data == 1)
			begin
				code = (6'h30);
			end
			else
			begin
				if (data == 2)
				begin
					code = (7'h6b);
				end
				else
				begin
					if (data == 3)
					begin
						code = (7'h79);
					end
					else
					begin
						if (data == 4)
						begin
							code = (6'h33);
						end
						else
						begin
							if (data == 5)
							begin
								code = (7'h5b);
							end
							else
							begin
								if (data == 6)
								begin
									code = (7'h5f);
								end
								else
								begin
									if (data == 7)
									begin
										code = (7'h72);
									end
									else
									begin
										if (data == 8)
										begin
											code = (7'h7f);
										end
										else
										begin
											if (data == 9)
											begin
												code = (7'h7b);
											end
											else
											begin
											end
										end
									end
								end
							end
						end
					end
				end
			end
		end
	end
endmodule

testベンチを書いた

module testbench;
	reg [3:0] data;
	wire [6:0] code;
	x u(.data(data), .code(code));
	initial
	begin
		$display(" data code");
		$monitor( "%h	%h", data, code);
		data = 4'h0; #10;
		data = 4'h1; #10;
		data = 4'h2; #10;
		data = 4'h3; #10;
		data = 4'h4; #10;
		data = 4'h5; #10;
		data = 4'h6; #10;
		data = 4'h7; #10;
		data = 4'h8; #10;
		data = 4'h9; #10;
		$finish;
	end
endmodule

実行結果

>iverilog block3.v

>vvp a.out
 data code
0       7e
1       30
2       6b
3       79
4       33
5       5b
6       5f
7       72
8       7f
9       7b
block3.v:99: $finish called at 100 (1s)

以上。