概要
micropythonでshrike-lite、やってみた。
ルネサスのGo Configure Software Hubは、腐ってる。
400行のverilogで落ちる。
再現手順
top.vを書いて、シンセサイズを押す。
エラーを吐かず、落ちる。
logは、どこ？
投入したtop.v
(* top *) module top ((* iopad_external_pin, clkbuf_inhibit *) input clk,
(* iopad_external_pin *) output clk_en,
(* iopad_external_pin *) input rst_n,
(* iopad_external_pin *) input spi_ss_n,
(* iopad_external_pin *) input spi_sck,
(* iopad_external_pin *) input spi_mosi,
(* iopad_external_pin *) output spi_miso,
(* iopad_external_pin *) output spi_miso_en
);
integer i;
reg [7:0] q [0:5];
reg [7:0] ram [0:3];
reg [11:0] rom [0:10];
reg [6:0] pc;
reg [6:0] adr;
reg [7:0] madr;
reg [7:0] out;
reg [7:0] tx_data_reg;
reg stop;
wire [11:0] code = rom[pc];
wire [3:0] op = code[11:8];
wire [7:0] opland = code[7:0];
wire [7:0] rx_data_wire;
wire rx_valid_pulse;
//assign led_en = 1'b1;
assign clk_en = 1'b1;
//assign outport = out;
spi_target #(.CPOL(1'b0), .CPHA(1'b0), .WIDTH(8), .LSB(1'b0))
u_spi_target (.i_clk(clk), .i_rst_n(rst_n), .i_enable(1'b1), .i_ss_n(spi_ss_n), .i_sck(spi_sck),
.i_mosi(spi_mosi), .o_miso(spi_miso), .o_miso_oe(spi_miso_en),
.o_rx_data(rx_data_wire), .o_rx_data_valid(rx_valid_pulse), .i_tx_data(tx_data_reg), .o_tx_data_hold());
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
tx_data_reg <= 8'h00;
end
else if (rx_valid_pulse)
begin
tx_data_reg <= rx_data_wire;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
stop <= 1'b0;
end
else if (rx_valid_pulse)
begin
if (rx_data_wire == 8'hAB)
stop <= 1'b1;
else if (rx_data_wire == 8'hFF)
stop <= 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rom[0] <= 12'h2_00;
rom[1] <= 12'h2_01;
rom[2] <= 12'hF_00;
rom[3] <= 12'hF_20;
rom[4] <= 12'h2_65;
rom[5] <= 12'hF_0F;
rom[6] <= 12'h3_3A;
rom[7] <= 12'h4_01;
rom[8] <= 12'hF_20;
rom[9] <= 12'h2_0F;
rom[10] <= 12'hF_04;
/*
rom[11] <= 12'h3_25;
rom[12] <= 12'h4_00;
rom[13] <= 12'hF_20;
rom[14] <= 12'h2_03;
rom[15] <= 12'hF_04;
rom[16] <= 12'h3_1B;
rom[17] <= 12'h4_00;
rom[18] <= 12'hF_20;
rom[19] <= 12'h2_05;
rom[20] <= 12'hF_04;
rom[21] <= 12'h3_2F;
rom[22] <= 12'h4_00;
rom[23] <= 12'hF_20;
rom[24] <= 12'hF_30;
rom[25] <= 12'h3_37;
rom[26] <= 12'h4_FF;
rom[27] <= 12'h2_46;
rom[28] <= 12'hF_31;
rom[29] <= 12'h2_69;
rom[30] <= 12'hF_31;
rom[31] <= 12'h2_7A;
rom[32] <= 12'hF_31;
rom[33] <= 12'h2_7A;
rom[34] <= 12'hF_31;
rom[35] <= 12'h3_37;
rom[36] <= 12'h4_FF;
rom[37] <= 12'h2_46;
rom[38] <= 12'hF_31;
rom[39] <= 12'h2_69;
rom[40] <= 12'hF_31;
rom[41] <= 12'h2_7A;
rom[42] <= 12'hF_31;
rom[43] <= 12'h2_7A;
rom[44] <= 12'hF_31;
rom[45] <= 12'h3_2F;
rom[46] <= 12'h4_FF;
rom[47] <= 12'h2_42;
rom[48] <= 12'hF_31;
rom[49] <= 12'h2_75;
rom[50] <= 12'hF_31;
rom[51] <= 12'h2_7A;
rom[52] <= 12'hF_31;
rom[53] <= 12'h2_7A;
rom[54] <= 12'hF_31;
rom[55] <= 12'hF_32;
rom[56] <= 12'h3_01;
rom[57] <= 12'h4_FF;
rom[58] <= 12'hF_21;
rom[59] <= 12'h0_00;
*/
for (i = 0; i < 6; i = i + 1)
q[i] <= 8'd0;
for (i = 0; i < 3; i = i + 1)
ram[i] <= 8'd0;
adr <= 0;
out <= 0;
pc <= 0;
end
else
begin
case (op)
4'h0:
pc <= pc;
4'h2:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= opland;
pc <= pc + 1;
end
4'h3:
begin
adr <= opland[5:0];
pc <= pc + 1;
end
4'h4:
begin
case (opland)
8'h00:
begin
if (q[0] == 8'd0)
pc <= adr;
else
pc <= pc + 1;
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h01:
begin
if (q[0] == 8'd1)
pc <= adr;
else
pc <= pc + 1;
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'hFF:
begin
pc <= adr;
end
default:
pc <= pc + 1;
endcase
end
4'h5:
begin
out <= q[0];
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
4'h6:
begin
case (opland)
8'h00:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= ram[q[0]];
pc <= pc + 1;
end
8'h01:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= ram[madr];
pc <= pc + 1;
end
default:
pc <= pc + 1;
endcase
end
4'h7:
begin
case (opland)
8'h00:
begin
ram[q[0]] <= q[0];
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
8'h01:
begin
ram[madr] <= q[0];
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
default:
pc <= pc + 1;
endcase
end
4'h8:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= q[0];
pc <= pc + 1;
end
4'h9:
begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
4'hA:
begin
madr <= opland;
pc <= pc + 1;
end
4'hF:
begin
case (opland)
8'h00:
begin
q[0] <= q[1] + q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h01:
begin
q[0] <= q[1] - q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h02:
begin
q[0] <= q[1] * q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h03:
begin
q[0] <= (q[0] != 0) ? q[1] / q[0] : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h04:
begin
q[0] <= (q[0] != 0) ? q[1] % q[0] : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h0F: // =
begin
q[0] <= (q[1] == q[0]) ? 8'd1 : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h10:
begin
q[0] <= (q[1] < q[0]) ? 8'd1 : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h11:
begin
q[0] <= (q[1] > q[0]) ? 8'd1 : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h12:
begin
q[0] <= (q[0] > q[1]) ? q[0] : q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h13:
begin
q[0] <= (q[0] < q[1]) ? q[0] : q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h14:
begin
q[0] <= q[1] & q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h15:
begin
q[0] <= q[1] | q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h16:
begin
q[0] <= ~q[0];
end
8'h20:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= q[0];
end
8'h21:
begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h22:
begin
q[0] <= q[1];
q[1] <= q[0];
end
8'h23:
begin
q[5] <= q[4];
q[4] <= q[3];
q[3] <= q[2];
q[2] <= q[1];
q[1] <= q[0];
q[0] <= q[1];
end
8'h24:
begin
q[0] <= q[2];
q[1] <= q[0];
q[2] <= q[1];
end
8'h25:
begin
q[5] <= q[4];
q[4] <= q[3];
q[3] <= q[2];
q[2] <= q[1];
q[1] <= q[0];
q[0] <= q[0];
end
8'h26:
begin
q[5] <= q[3];
q[4] <= q[2];
q[3] <= q[1];
q[2] <= q[0];
q[1] <= q[1];
q[0] <= q[0];
end
8'h52:
begin
q[0] <= ram[q[0] + 8'd1];
end
8'h60:
begin
q[0] <= q[0] - 8'd1;
if (q[0] != 8'd1)
begin
pc <= adr - 6'd1;
end
end
8'h30:
begin
$write("%d ", q[0]);
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h31:
begin
$write("%c", q[0]);
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h32:
begin
$display("");
end
8'h33:
begin
$write(" ");
end
default: ;
endcase
if (opland != 8'h60 || q[0] == 8'd1)
begin
pc <= pc + 1;
end
end
default:
pc <= pc + 1;
endcase
end
end
endmodule
削って落ちないコード
300行
(* top *) module top ((* iopad_external_pin, clkbuf_inhibit *) input clk,
(* iopad_external_pin *) output clk_en,
(* iopad_external_pin *) input rst_n,
(* iopad_external_pin *) input spi_ss_n,
(* iopad_external_pin *) input spi_sck,
(* iopad_external_pin *) input spi_mosi,
(* iopad_external_pin *) output spi_miso,
(* iopad_external_pin *) output spi_miso_en
);
integer i;
reg [7:0] q [0:5];
reg [6:0] pc;
reg [6:0] adr;
reg [7:0] madr;
reg [7:0] out;
reg [7:0] tx_data_reg;
reg stop;
wire [11:0] code; //= rom[pc];
wire [3:0] op = code[11:8];
wire [7:0] opland = code[7:0];
wire [7:0] rx_data_wire;
wire rx_valid_pulse;
assign clk_en = 1'b1;
spi_target #(.CPOL(1'b0), .CPHA(1'b0), .WIDTH(8), .LSB(1'b0))
u_spi_target (.i_clk(clk), .i_rst_n(rst_n), .i_enable(1'b1), .i_ss_n(spi_ss_n), .i_sck(spi_sck),
.i_mosi(spi_mosi), .o_miso(spi_miso), .o_miso_oe(spi_miso_en),
.o_rx_data(rx_data_wire), .o_rx_data_valid(rx_valid_pulse), .i_tx_data(tx_data_reg), .o_tx_data_hold());
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tx_data_reg <= 8'h00;
end
else if (rx_valid_pulse) begin
tx_data_reg <= rx_data_wire;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
stop <= 1'b0;
end
else if (rx_valid_pulse) begin
if (rx_data_wire == 8'hAB)
stop <= 1'b1;
else if (rx_data_wire == 8'hFF)
stop <= 1'b0;
end
end
// 感度リストに or negedge rst_n を追加し、リセット動作の整合性を確保
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
// integerを使用したループ初期化
for (i = 0; i < 6; i = i + 1)
q[i] <= 8'd0;
adr <= 0;
out <= 0;
pc <= 0;
madr <= 0;
end
else
begin
case (op)
4'h0:
pc <= pc;
4'h2:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= opland;
pc <= pc + 1;
end
4'h3:
begin
adr <= opland[5:0];
pc <= pc + 1;
end
4'h4:
begin
case (opland)
8'h00:
begin
if (q[0] == 8'd0)
pc <= adr;
else
pc <= pc + 1;
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h01:
begin
if (q[0] == 8'd1)
pc <= adr;
else
pc <= pc + 1;
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'hFF:
begin
pc <= adr;
end
default:
pc <= pc + 1;
endcase
end
4'h5:
begin
out <= q[0];
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
4'h6:
begin
case (opland)
8'h00: pc <= pc + 1;
8'h01: pc <= pc + 1;
default: pc <= pc + 1;
endcase
end
4'h7:
begin
case (opland)
8'h00:
begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
8'h01:
begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
default:
pc <= pc + 1;
endcase
end
4'h8:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= q[0];
pc <= pc + 1;
end
4'h9:
begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
pc <= pc + 1;
end
4'hA:
begin
madr <= opland;
pc <= pc + 1;
end
4'hF:
begin
case (opland)
8'h00:
begin
q[0] <= q[1] + q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h01:
begin
q[0] <= q[1] - q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h02:
begin
q[0] <= q[1] * q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h03: // GreenPAKの規模では除算は論理合成エラーやフリーズの原因になりやすいです
begin
q[0] <= (q[0] != 0) ? q[1] / q[0] : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h04: // 剰余も同様に莫大なリソースを消費します
begin
q[0] <= (q[0] != 0) ? q[1] % q[0] : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h0F: // =
begin
q[0] <= (q[1] == q[0]) ? 8'd1 : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h10:
begin
q[0] <= (q[1] < q[0]) ? 8'd1 : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h11:
begin
q[0] <= (q[1] > q[0]) ? 8'd1 : 8'd0;
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h12:
begin
q[0] <= (q[0] > q[1]) ? q[0] : q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h13:
begin
q[0] <= (q[1] < q[0]) ? q[1] : q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h14:
begin
q[0] <= q[1] & q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h15:
begin
q[0] <= q[1] | q[0];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h16:
begin
q[0] <= ~q[0];
end
8'h20:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= q[0];
end
8'h21:
begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h22:
begin
q[0] <= q[1];
q[1] <= q[0];
end
8'h23:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= q[1];
end
8'h24:
begin
q[0] <= q[2];
q[1] <= q[0];
q[2] <= q[1];
end
8'h25:
begin
q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0];
q[0] <= q[0];
end
8'h26:
begin
q[5] <= q[3]; q[4] <= q[2]; q[3] <= q[1]; q[2] <= q[0];
q[1] <= q[1]; q[0] <= q[0];
end
8'h52: ;
8'h60:
begin
q[0] <= q[0] - 8'd1;
if (q[0] != 8'd1)
begin
pc <= adr - 6'd1;
end
end
// シミュレーション専用タスク（$write, $display）をすべて削除（または空に変更）
8'h30: begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h31: begin
q[0] <= q[1];
q[1] <= q[2]; q[2] <= q[3]; q[3] <= q[4]; q[4] <= q[5]; q[5] <= 8'd0;
end
8'h32: ;
8'h33: ;
default: ;
endcase
if (opland != 8'h60 || q[0] == 8'd1)
begin
pc <= pc + 1;
end
end
default:
pc <= pc + 1;
endcase
end
end
endmodule
以上。