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ビジュアルプログラミングで高位合成 その3

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概要

ビジュアルプログラミングで組み合わせ回路を組み立てて、シュミレーションして、verilogを生成します。
高位合成です。
検証編

テストベンチを作成する。


module x(input In0, input In1, output Out0);
	assign Out0 = (In1  ^ In0);
endmodule

module test;
	reg In0;
	reg In1;
	x u(.In0(In0), .In1(In1), .Out0(Out0));
	initial
	begin
		$display(" In0 In1 Out0");
		$monitor(" %b  %b  %b", In0, In1, Out0);
		In0 = 0;
		In1 = 0;
	#10;
		In0 = 0;
		In1 = 1;
	#10;
		In0 = 1;
		In1 = 0;
	#10;
		In0 = 1;
		In1 = 1;
	#10;
		$finish;
	end
endmodule

iverilogでシュミレーションする。

>iverilog xor3.v

>vvp a.out
 In0 In1 Out0
 0  0  0
 0  1  1
 1  0  1
 1  1  0
xor3.v:27: $finish called at 40 (1s)

以上。

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