- Yosuke Toyota@youtoy
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- Akihiko SHIRAI@o_ob
éããããã®ãšã³ã¿ã¡å士ã§ã ã¡ã¿ããŒã¹ã®äŒç€Ÿã§R&Dãªã©ããŠãããŸã [YouTube] http://j.mp/VRSYT [note] https://note.com/reality_eng/m/m394ac85738b5 [Lab] https://vr.gree.net/lab/
- Manabu Araki@ArakiManabu
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- Dr. Kiyoshi Ogawa@kaizen_nagoya
I'm a network designer.I work on TOPPERS SmallestSetProfile Kernel,MISRA-C/C++, STARC RTL Design StyleGuide (Verilog-HDL), and HAZOP.I was an editor of ISO/IEC 15504.