Detailed Explanation of Key MOSFET Equations

1. Threshold Voltage Equation

$$
V_T = \phi_{ms} + 2\phi_f + \frac{\sqrt{4q \varepsilon_s N_A 2\phi_f}}{C_{ox}}
$$

Meaning:

• $V_T$: Minimum gate voltage required to invert the channel.
• $\phi_{ms}$: Work function difference (metal–semiconductor)
• $\phi_f$: Fermi potential; defines intrinsic energy level separation.
• $q$: Elementary charge
• $\varepsilon_s$: Permittivity of the semiconductor
• $N_A$: Substrate doping concentration (p-type for NMOS)
• $C_{ox}$: Gate oxide capacitance per unit area

Physical Insight:

This equation models the voltage needed to create an inversion layer. It combines electrostatic requirements (2ϕ_f), material work function difference (ϕ_ms), and the electric field needed to balance depletion charge.

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2. Linear Region Drain Current (Triode)

$$
I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_T) V_{DS} - \frac{1}{2} V_{DS}^2 \right]
$$

Meaning:

• $\mu_n$: Electron mobility (NMOS)
• $W/L$: Width/length ratio (geometry scaling factor)
• $V_{GS}$: Gate-to-source voltage
• $V_{DS}$: Drain-to-source voltage
• $V_T$: Threshold voltage

When valid:

$$
0 < V_{DS} < V_{GS} - V_T
$$

Physical Insight:

• Derived by integrating charge and velocity across the channel.
• As $V_{DS}$ increases, the channel becomes non-uniform (from source to drain).
• The current increases linearly for small $V_{DS}$, hence "linear/triode" region.

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3. Saturation Region Drain Current

$$
I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2
$$

When valid:

$$
V_{DS} \geq V_{GS} - V_T
$$

Physical Insight:

• At high $V_{DS}$, the channel pinches off near the drain.
• Carriers saturate in velocity or cannot be injected beyond the pinch-off.
• Current becomes independent of $V_{DS}$, and only depends on $V_{GS}$.

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4. Subthreshold Current (Weak Inversion)

$$
I_D = I_0 \exp\left( \frac{V_{GS} - V_T}{n V_T} \right) \left(1 - \exp\left( -\frac{V_{DS}}{V_T} \right)\right)
$$

Meaning:

• $I_0$: Device-dependent scaling factor
• $V_T$ (thermal): $\approx 25,\text{mV}$ at 300K
• $n$: Subthreshold slope factor (typically 1.1–1.5)

Physical Insight:

• Even when $V_{GS} < V_T$, thermionic carriers can cross the barrier.
• Important for leakage power in digital circuits.
• Current increases exponentially with $V_{GS}$.

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5. Channel Length Modulation (CLM)

$$
I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2 (1 + \lambda V_{DS})
$$

Meaning:

• $\lambda$: Channel length modulation coefficient (analogous to Early effect in BJTs)

Physical Insight:

• As $V_{DS}$ increases in saturation, the pinch-off point moves toward the source.
• Effective channel shortens, reducing resistance.
• Result: small increase in $I_D$ with $V_{DS}$, even in saturation.

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6. Small Signal Model Parameters

Transconductance:

$$
g_m = \frac{\partial I_D}{\partial V_{GS}} = \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)
$$

Or:

$$
g_m = \sqrt{2 \mu_n C_{ox} \frac{W}{L} I_D}
$$

Output resistance:

$$
r_o = \frac{1}{\lambda I_D}
$$

Body effect transconductance:

$$
g_{mb} = \eta g_m \quad \text{with } \eta \approx 0.3\text{–}0.4
$$

Insight:

• These parameters model linear small perturbations around the operating point.
• Used in AC analysis, gain calculation, and impedance estimation.

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7. Capacitance Between Terminals

Gate-to-Source and Gate-to-Drain Capacitances:

• Triode Region:

  $$
  C_{GS} = C_{GD} = \frac{1}{2} W L C_{ox}
  $$

• Saturation Region:

  $$
  C_{GS} \approx \frac{2}{3} W L C_{ox}, \quad C_{GD} \rightarrow 0
  $$

Junction Capacitances:

• Junction depletion capacitance (bottom + sidewall):

  $$
  C_{j} = A C_j + P C_{jsw}
  $$

  • $A$: Area of junction
  • $P$: Perimeter
  • $C_j, C_{jsw}$: Bottom and sidewall junction capacitance densities

Physical Insight:

• Capacitances affect speed, power, and noise margin.
• Shorter or folded layouts reduce junction area/perimeter, lowering parasitics.

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