■ (1) IC Manufacturing: Front-End Process (Wafer Process)
◉ Overview
The front-end process refers to the formation of circuit elements such as transistors, resistors, and capacitors on a silicon wafer. This process involves repeated cycles of thin-film deposition, photolithography, doping, and etching to build up the multilayered structure of the integrated circuit.
◉ Process Steps
1. Thin-Film Deposition
Various films—such as insulating layers, polysilicon, or metal conductors—are formed on the wafer using physical and chemical methods:
- Thermal Oxidation: Forms silicon dioxide (SiO₂) by oxidizing the silicon surface at high temperatures.
- CVD (Chemical Vapor Deposition): Deposits insulating or conductive films by inducing chemical reactions of gaseous precursors.
- Sputtering: A physical vapor deposition technique where high-energy ions knock atoms from a target material to form a film on the wafer.
2. Photolithography
This is the micro-patterning process to transfer circuit layouts onto the wafer:
- Photoresist Coating: A light-sensitive chemical (photoresist) is spin-coated onto the wafer.
- Exposure: Ultraviolet (UV) light is shone through a photomask to expose selected areas of the resist.
- Development: The exposed (or unexposed, depending on resist type) areas are dissolved and removed using a developer solution.
3. Etching
This step removes exposed areas of the thin film to form the desired circuit pattern:
- Dry Etching: Uses plasma to etch materials with high anisotropy.
- Wet Etching: Employs chemical solutions to dissolve materials in a more isotropic manner.
4. Doping (Impurity Implantation)
This modifies the electrical characteristics of silicon by introducing dopants:
- Ion Implantation: Ions of dopant elements (e.g., boron, phosphorus) are accelerated into the wafer.
- Annealing: A heat treatment that activates the dopants and repairs damage caused by ion bombardment.
5. Photoresist Removal
After processing, the residual photoresist is completely stripped off to prepare the wafer for the next layer.
◉ Post-Device Formation Steps
• Wafer-Level Testing
Each die on the wafer is tested for basic electrical properties to identify defective chips early in the process.
• Back Grinding
The backside of the wafer is thinned down via grinding to enable easier packaging and better thermal performance.
• Pre-Wafer Test / Laser Trimming
For high-precision analog circuits, trimming is done by cutting built-in laser fuses to fine-tune performance parameters based on initial measurements.
• Wafer Probing (Probe Test)
Needle-like probes are used to make contact with pads on each die to conduct electrical tests before dicing.
■ (2) IC Manufacturing: Back-End Process (Packaging)
◉ Overview
The back-end process involves cutting individual IC chips from the processed wafer and encapsulating them into protective packages that enable connection to external circuits and systems.
◉ Process Steps
1. Dicing
The wafer is sliced into individual dies using a high-speed diamond blade or laser.
2. Die Bonding
Each chip is attached to a lead frame or substrate using an adhesive or solder material.
3. Wire Bonding
Gold or aluminum wires connect the chip’s internal pads to the external leads of the package with extreme precision.
4. Molding
The chip and wire connections are encapsulated in a resin (often epoxy) to provide mechanical strength and protection against environmental factors.
5. Solder Plating
Leads are plated with solder (typically tin-based) to enable soldering to printed circuit boards (PCBs).
6. Marking
The package is labeled with the part number, manufacturer name, and batch information using laser or ink printing.
7. Trimming and Forming
Leads are trimmed to the correct length and shaped (e.g., bent or gull-winged) for the intended package style (DIP, QFP, etc.).
8. Final Electrical Test
Each completed IC package undergoes functional testing to verify performance under standard operating conditions.
9. Visual Inspection / Packaging / Shipment
Appearance is checked for cracks, dirt, or other defects, then the ICs are packed and shipped.
◉ Purpose of Packaging
- Protection: Shields the silicon die from moisture, oxidation, and mechanical stress.
- Connectivity: Provides external terminals for integration with other circuitry.
- Heat Dissipation: Helps in releasing generated heat efficiently.
- Standardization: Facilitates automated assembly with standardized shapes and pin configurations.
■ (3) Photomask Fabrication Process
◉ Purpose
Photomasks are high-precision plates used in photolithography to transfer IC layout patterns onto wafers. Each mask corresponds to one circuit layer, and modern ICs may require dozens of such masks.
◉ Process Steps
1. Mask Blank Preparation
A glass (usually quartz) substrate is coated with a thin film of chromium or chromium oxide by sputtering to serve as the base layer for patterning.
2. Photoresist Coating
A uniform layer of photoresist (positive or negative type) is spin-coated on the chromium surface.
3. Electron Beam (EB) Writing
Using layout data (e.g., GDS-II format), an electron beam directly writes the circuit pattern onto the resist with nanometer-level precision.
4. Development and Etching
After exposure, the resist is developed, and exposed areas are etched away, typically by chemical etching, to remove the chromium film in the desired pattern.
5. Resist Stripping
The remaining resist is stripped off, leaving behind the clean patterned chromium on the glass.
6. Defect Inspection and Repair
The pattern is thoroughly inspected using high-resolution imaging tools. Any defects are corrected manually or automatically to ensure yield and quality.
7. Pellicle Attachment
A transparent pellicle (dust-protection film) is mounted slightly above the mask surface to protect it during exposure steps.
8. Shipping
The finished photomask is carefully packaged and delivered to semiconductor fabs for use in wafer production.