Quartus Prime 18.1 で Frame Reader を復活させる

概要

DE10-nano を初めとした Intel SoCFPGA を使って Linux Desktop を表示させたい場合、Frame Buffer をFPGA 側に実装する必要がありますが、最近の Quartus Prime から Frame Reader IP コアが廃止になってしまったため、有償の IP を使わなければなりませんでした。しかし、Quartus Prime Lite/Standard 18.1 に Frame Reader IP コアのソースが残っていましたので、これを Quartus Prime Lite 18.1 でコンパイルする事ができます。

手順

(1) Quartus Prime Lite 18.1 のインストールフォルダから frame_reader フォルダを探します。デフォルトでのインストールなら C:\intelFPGA_lite\18.1\ip\altera の下にあります。

(2) コンパイルしたい Quartus プロジェクトの下にフォルダごとコピーします。ip フォルダとかがあれば、その下でも問題ありません。

(3) <コピーしたフォルダ>\frame_reader\full_ip\frame_reader の中に alt_vip_vfr_hw.tcl と言うファイルがありますので、このファイルの内容を下記のコードに全て置き換えます。

(4) Quartus プロジェクトを開いて、Platform Designer を起動し、IP Catalog に下記のように表示されれば OK です。

(5) 既に Frame Reader を実装しているシステムであれば、このまま Generate して再コンパイルすれば 18.1の SOF が完成します。

(6) Frame Reader を実装していないシステムであれば、Frame Reader を Add してパラメタを設定すれば OK です。GUI は昔の Frame Reader と同じです。（ Linux Desktop の実装の仕方は必要があれば説明しますが、ここでは詳しくは説明しません）

package require -exact qsys 18.1


# 
# module alt_vip_vfr
# 
set_module_property DESCRIPTION "The Frame Reader Megacore can be used to read a video stream from video frames stored a memory buffer"
set_module_property NAME alt_vip_vfr
set_module_property VERSION 18.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP test
set_module_property AUTHOR "Intel Corporation"
set_module_property DISPLAY_NAME "Frame Reader"
set_module_property DATASHEET_URL http://www.altera.com/literature/ug/ug_vip.pdf
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL alt_vipvfr131_vfr
set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file alt_vipvfr131_vfr.v VERILOG PATH src_hdl/alt_vipvfr131_vfr.v TOP_LEVEL_FILE
add_fileset_file alt_vipvfr131_vfr_controller.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_controller.v
add_fileset_file alt_vipvfr131_vfr_control_packet_encoder.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v
add_fileset_file alt_vipvfr131_prc.v VERILOG PATH src_hdl/alt_vipvfr131_prc.v
add_fileset_file alt_vipvfr131_prc_core.v VERILOG PATH src_hdl/alt_vipvfr131_prc_core.v
add_fileset_file alt_vipvfr131_prc_read_master.v VERILOG PATH src_hdl/alt_vipvfr131_prc_read_master.v
add_fileset_file alt_vipvfr131_common_package.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_package.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_master.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_master.v
add_fileset_file alt_vipvfr131_common_unpack_data.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_unpack_data.v
add_fileset_file alt_vipvfr131_common_avalon_mm_slave.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_slave.v
add_fileset_file alt_vipvfr131_common_stream_output.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_stream_output.v
add_fileset_file alt_vipvfr131_common_pulling_width_adapter.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd
add_fileset_file alt_vipvfr131_common_general_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_general_fifo.vhd
add_fileset_file alt_vipvfr131_common_fifo_usedw_calculator.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd
add_fileset_file alt_vipvfr131_common_gray_clock_crosser.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd
add_fileset_file alt_vipvfr131_common_std_logic_vector_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd
add_fileset_file alt_vipvfr131_common_one_bit_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_one_bit_delay.vhd
add_fileset_file alt_vipvfr131_common_logic_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_logic_fifo.vhd
add_fileset_file alt_vipvfr131_common_ram_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_ram_fifo.vhd
add_fileset_file alt_vipvfr131_vfr.sdc SDC PATH alt_vipvfr131_vfr.sdc

add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
set_fileset_property sim_verilog TOP_LEVEL alt_vipvfr131_vfr
set_fileset_property sim_verilog ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_verilog ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file alt_vipvfr131_vfr.v VERILOG PATH src_hdl/alt_vipvfr131_vfr.v
add_fileset_file alt_vipvfr131_vfr_controller.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_controller.v
add_fileset_file alt_vipvfr131_vfr_control_packet_encoder.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v
add_fileset_file alt_vipvfr131_prc.v VERILOG PATH src_hdl/alt_vipvfr131_prc.v
add_fileset_file alt_vipvfr131_prc_core.v VERILOG PATH src_hdl/alt_vipvfr131_prc_core.v
add_fileset_file alt_vipvfr131_prc_read_master.v VERILOG PATH src_hdl/alt_vipvfr131_prc_read_master.v
add_fileset_file alt_vipvfr131_common_package.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_package.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_master.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_master.v
add_fileset_file alt_vipvfr131_common_unpack_data.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_unpack_data.v
add_fileset_file alt_vipvfr131_common_avalon_mm_slave.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_slave.v
add_fileset_file alt_vipvfr131_common_stream_output.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_stream_output.v
add_fileset_file alt_vipvfr131_common_pulling_width_adapter.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd
add_fileset_file alt_vipvfr131_common_general_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_general_fifo.vhd
add_fileset_file alt_vipvfr131_common_fifo_usedw_calculator.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd
add_fileset_file alt_vipvfr131_common_gray_clock_crosser.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd
add_fileset_file alt_vipvfr131_common_std_logic_vector_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd
add_fileset_file alt_vipvfr131_common_one_bit_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_one_bit_delay.vhd
add_fileset_file alt_vipvfr131_common_logic_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_logic_fifo.vhd
add_fileset_file alt_vipvfr131_common_ram_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_ram_fifo.vhd
add_fileset_file alt_vipvfr131_vfr.sdc SDC PATH alt_vipvfr131_vfr.sdc

add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation"
set_fileset_property sim_vhdl TOP_LEVEL alt_vipvfr131_vfr
set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file alt_vipvfr131_vfr.v VERILOG PATH src_hdl/alt_vipvfr131_vfr.v
add_fileset_file alt_vipvfr131_vfr_controller.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_controller.v
add_fileset_file alt_vipvfr131_vfr_control_packet_encoder.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v
add_fileset_file alt_vipvfr131_prc.v VERILOG PATH src_hdl/alt_vipvfr131_prc.v
add_fileset_file alt_vipvfr131_prc_core.v VERILOG PATH src_hdl/alt_vipvfr131_prc_core.v
add_fileset_file alt_vipvfr131_prc_read_master.v VERILOG PATH src_hdl/alt_vipvfr131_prc_read_master.v
add_fileset_file alt_vipvfr131_common_package.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_package.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_master.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_master.v
add_fileset_file alt_vipvfr131_common_unpack_data.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_unpack_data.v
add_fileset_file alt_vipvfr131_common_avalon_mm_slave.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_slave.v
add_fileset_file alt_vipvfr131_common_stream_output.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_stream_output.v
add_fileset_file alt_vipvfr131_common_pulling_width_adapter.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd
add_fileset_file alt_vipvfr131_common_general_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_general_fifo.vhd
add_fileset_file alt_vipvfr131_common_fifo_usedw_calculator.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd
add_fileset_file alt_vipvfr131_common_gray_clock_crosser.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd
add_fileset_file alt_vipvfr131_common_std_logic_vector_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd
add_fileset_file alt_vipvfr131_common_one_bit_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_one_bit_delay.vhd
add_fileset_file alt_vipvfr131_common_logic_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_logic_fifo.vhd
add_fileset_file alt_vipvfr131_common_ram_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_ram_fifo.vhd


# 
# documentation links
# 
add_documentation_link "Data Sheet" http://www.altera.com/literature/ug/ug_vip.pdf
add_documentation_link "Data Sheet" http://www.altera.com/literature/ug/ug_vip.pdf


# 
# parameters
# 
add_parameter FAMILY STRING "Cyclone IV" "Current device family selected"
set_parameter_property FAMILY DEFAULT_VALUE "Cyclone IV"
set_parameter_property FAMILY DISPLAY_NAME "Device family selected"
set_parameter_property FAMILY TYPE STRING
set_parameter_property FAMILY VISIBLE false
set_parameter_property FAMILY UNITS None
set_parameter_property FAMILY DESCRIPTION "Current device family selected"
set_parameter_property FAMILY AFFECTS_GENERATION false
set_parameter_property FAMILY SYSTEM_INFO_TYPE DEVICE_FAMILY
add_parameter BITS_PER_PIXEL_PER_COLOR_PLANE INTEGER 8 "The number of bits used per pixel, per color plane"
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE DEFAULT_VALUE 8
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE DISPLAY_NAME "Bits per pixel per color plane"
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE TYPE INTEGER
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE UNITS None
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE ALLOWED_RANGES 4:16
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE DESCRIPTION "The number of bits used per pixel, per color plane"
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE AFFECTS_GENERATION false
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE HDL_PARAMETER true
add_parameter NUMBER_OF_CHANNELS_IN_PARALLEL INTEGER 3 "The number color planes transmitted in parallel"
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL DEFAULT_VALUE 3
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL DISPLAY_NAME "Number of color planes in parallel"
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL TYPE INTEGER
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL UNITS None
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL ALLOWED_RANGES 1:4
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL DESCRIPTION "The number color planes transmitted in parallel"
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL AFFECTS_GENERATION false
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL HDL_PARAMETER true
add_parameter NUMBER_OF_CHANNELS_IN_SEQUENCE INTEGER 1 "The number color planes transmitted in sequence"
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE DEFAULT_VALUE 1
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE DISPLAY_NAME "Number of color planes in sequence"
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE TYPE INTEGER
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE UNITS None
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE ALLOWED_RANGES 1:3
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE DESCRIPTION "The number color planes transmitted in sequence"
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE AFFECTS_GENERATION false
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE HDL_PARAMETER true
add_parameter MAX_IMAGE_WIDTH INTEGER 640 "The maximum width of images / video frames"
set_parameter_property MAX_IMAGE_WIDTH DEFAULT_VALUE 640
set_parameter_property MAX_IMAGE_WIDTH DISPLAY_NAME "Maximum Image width"
set_parameter_property MAX_IMAGE_WIDTH TYPE INTEGER
set_parameter_property MAX_IMAGE_WIDTH UNITS None
set_parameter_property MAX_IMAGE_WIDTH ALLOWED_RANGES 32:2600
set_parameter_property MAX_IMAGE_WIDTH DESCRIPTION "The maximum width of images / video frames"
set_parameter_property MAX_IMAGE_WIDTH AFFECTS_GENERATION false
set_parameter_property MAX_IMAGE_WIDTH HDL_PARAMETER true
add_parameter MAX_IMAGE_HEIGHT INTEGER 480 "The maximum height of images / video frames"
set_parameter_property MAX_IMAGE_HEIGHT DEFAULT_VALUE 480
set_parameter_property MAX_IMAGE_HEIGHT DISPLAY_NAME "Maximum Image height"
set_parameter_property MAX_IMAGE_HEIGHT TYPE INTEGER
set_parameter_property MAX_IMAGE_HEIGHT UNITS None
set_parameter_property MAX_IMAGE_HEIGHT ALLOWED_RANGES 32:2600
set_parameter_property MAX_IMAGE_HEIGHT DESCRIPTION "The maximum height of images / video frames"
set_parameter_property MAX_IMAGE_HEIGHT AFFECTS_GENERATION false
set_parameter_property MAX_IMAGE_HEIGHT HDL_PARAMETER true
add_parameter MEM_PORT_WIDTH INTEGER 256 "The width in bits of the master port"
set_parameter_property MEM_PORT_WIDTH DEFAULT_VALUE 256
set_parameter_property MEM_PORT_WIDTH DISPLAY_NAME "Master port width"
set_parameter_property MEM_PORT_WIDTH TYPE INTEGER
set_parameter_property MEM_PORT_WIDTH UNITS None
set_parameter_property MEM_PORT_WIDTH ALLOWED_RANGES 16:256
set_parameter_property MEM_PORT_WIDTH DESCRIPTION "The width in bits of the master port"
set_parameter_property MEM_PORT_WIDTH AFFECTS_GENERATION false
set_parameter_property MEM_PORT_WIDTH HDL_PARAMETER true
add_parameter RMASTER_FIFO_DEPTH INTEGER 64 "The depth of the read master FIFO"
set_parameter_property RMASTER_FIFO_DEPTH DEFAULT_VALUE 64
set_parameter_property RMASTER_FIFO_DEPTH DISPLAY_NAME "Read master FIFO depth"
set_parameter_property RMASTER_FIFO_DEPTH TYPE INTEGER
set_parameter_property RMASTER_FIFO_DEPTH UNITS None
set_parameter_property RMASTER_FIFO_DEPTH ALLOWED_RANGES 8:1024
set_parameter_property RMASTER_FIFO_DEPTH DESCRIPTION "The depth of the read master FIFO"
set_parameter_property RMASTER_FIFO_DEPTH AFFECTS_GENERATION false
set_parameter_property RMASTER_FIFO_DEPTH HDL_PARAMETER true
add_parameter RMASTER_BURST_TARGET INTEGER 32 "The target burst size of the read master"
set_parameter_property RMASTER_BURST_TARGET DEFAULT_VALUE 32
set_parameter_property RMASTER_BURST_TARGET DISPLAY_NAME "Read master FIFO burst target"
set_parameter_property RMASTER_BURST_TARGET TYPE INTEGER
set_parameter_property RMASTER_BURST_TARGET UNITS None
set_parameter_property RMASTER_BURST_TARGET ALLOWED_RANGES 2:256
set_parameter_property RMASTER_BURST_TARGET DESCRIPTION "The target burst size of the read master"
set_parameter_property RMASTER_BURST_TARGET AFFECTS_GENERATION false
set_parameter_property RMASTER_BURST_TARGET HDL_PARAMETER true
add_parameter CLOCKS_ARE_SEPARATE INTEGER 1 "Use separate clock for the Avalon-MM master interface"
set_parameter_property CLOCKS_ARE_SEPARATE DEFAULT_VALUE 1
set_parameter_property CLOCKS_ARE_SEPARATE DISPLAY_NAME "Use separate clock for the Avalon-MM master interface"
set_parameter_property CLOCKS_ARE_SEPARATE TYPE INTEGER
set_parameter_property CLOCKS_ARE_SEPARATE UNITS None
set_parameter_property CLOCKS_ARE_SEPARATE ALLOWED_RANGES 0:1
set_parameter_property CLOCKS_ARE_SEPARATE DESCRIPTION "Use separate clock for the Avalon-MM master interface"
set_parameter_property CLOCKS_ARE_SEPARATE DISPLAY_HINT boolean
set_parameter_property CLOCKS_ARE_SEPARATE AFFECTS_GENERATION false
set_parameter_property CLOCKS_ARE_SEPARATE HDL_PARAMETER true


# 
# display items
# 


# 
# connection point clock_reset
# 
add_interface clock_reset clock end
set_interface_property clock_reset clockRate 0
set_interface_property clock_reset ENABLED true
set_interface_property clock_reset EXPORT_OF ""
set_interface_property clock_reset PORT_NAME_MAP ""
set_interface_property clock_reset CMSIS_SVD_VARIABLES ""
set_interface_property clock_reset SVD_ADDRESS_GROUP ""

add_interface_port clock_reset clock clk Input 1


# 
# connection point clock_reset_reset
# 
add_interface clock_reset_reset reset end
set_interface_property clock_reset_reset associatedClock clock_reset
set_interface_property clock_reset_reset synchronousEdges DEASSERT
set_interface_property clock_reset_reset ENABLED true
set_interface_property clock_reset_reset EXPORT_OF ""
set_interface_property clock_reset_reset PORT_NAME_MAP ""
set_interface_property clock_reset_reset CMSIS_SVD_VARIABLES ""
set_interface_property clock_reset_reset SVD_ADDRESS_GROUP ""

add_interface_port clock_reset_reset reset reset Input 1


# 
# connection point clock_master
# 
add_interface clock_master clock end
set_interface_property clock_master clockRate 0
set_interface_property clock_master ENABLED true
set_interface_property clock_master EXPORT_OF ""
set_interface_property clock_master PORT_NAME_MAP ""
set_interface_property clock_master CMSIS_SVD_VARIABLES ""
set_interface_property clock_master SVD_ADDRESS_GROUP ""

add_interface_port clock_master master_clock clk Input 1


# 
# connection point clock_master_reset
# 
add_interface clock_master_reset reset end
set_interface_property clock_master_reset associatedClock clock_master
set_interface_property clock_master_reset synchronousEdges DEASSERT
set_interface_property clock_master_reset ENABLED true
set_interface_property clock_master_reset EXPORT_OF ""
set_interface_property clock_master_reset PORT_NAME_MAP ""
set_interface_property clock_master_reset CMSIS_SVD_VARIABLES ""
set_interface_property clock_master_reset SVD_ADDRESS_GROUP ""

add_interface_port clock_master_reset master_reset reset Input 1


# 
# connection point avalon_slave
# 
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressAlignment NATIVE
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock_reset
set_interface_property avalon_slave associatedReset clock_reset_reset
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 1
set_interface_property avalon_slave readWaitStates 0
set_interface_property avalon_slave readWaitTime 0
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave slave_address address Input 5
add_interface_port avalon_slave slave_write write Input 1
add_interface_port avalon_slave slave_writedata writedata Input 32
add_interface_port avalon_slave slave_read read Input 1
add_interface_port avalon_slave slave_readdata readdata Output 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0


# 
# connection point interrupt_sender
# 
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave
set_interface_property interrupt_sender associatedClock clock_reset
set_interface_property interrupt_sender associatedReset clock_reset_reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""

add_interface_port interrupt_sender slave_irq irq Output 1

# -- Dynamic Ports (elaboration callback) --
set_module_property ELABORATION_CALLBACK vfr_elaboration_callback
proc vfr_elaboration_callback {} {
  	# +-----------------------------------
	# | connection point avalon_streaming_source
	# | 
	set color_planes_in_parallel [get_parameter_value NUMBER_OF_CHANNELS_IN_PARALLEL]
	set bps [get_parameter_value BITS_PER_PIXEL_PER_COLOR_PLANE]
	set data_width [expr $bps * $color_planes_in_parallel]
	
	add_interface avalon_streaming_source avalon_streaming start
	set_interface_property avalon_streaming_source dataBitsPerSymbol $bps
	set_interface_property avalon_streaming_source symbolsPerBeat $color_planes_in_parallel
	set_interface_property avalon_streaming_source errorDescriptor ""
	set_interface_property avalon_streaming_source maxChannel 0
	set_interface_property avalon_streaming_source readyLatency 1
	
	add_interface_port avalon_streaming_source dout_data data Output $data_width
	add_interface_port avalon_streaming_source dout_valid valid Output 1
	add_interface_port avalon_streaming_source dout_ready ready Input 1
	add_interface_port avalon_streaming_source dout_startofpacket startofpacket Output 1
	add_interface_port avalon_streaming_source dout_endofpacket endofpacket Output 1	
	
	set_interface_property avalon_streaming_source ASSOCIATED_CLOCK clock_reset
	set_interface_property avalon_streaming_source ENABLED true	
	# | 
	# +-----------------------------------
	
	# +-----------------------------------
	# | connection point avalon_master
	# | 
	set mem_port_width [get_parameter_value MEM_PORT_WIDTH]
	add_interface avalon_master avalon start
	set_interface_property avalon_master burstOnBurstBoundariesOnly false
	set_interface_property avalon_master doStreamReads false
	set_interface_property avalon_master doStreamWrites false
	set_interface_property avalon_master linewrapBursts false
	
	set_interface_property avalon_master ASSOCIATED_CLOCK clock_master
	set_interface_property avalon_master ENABLED true
	
	set burst_target [get_parameter_value RMASTER_BURST_TARGET]
	add_interface_port avalon_master master_address address Output 32
	add_interface_port avalon_master master_burstcount burstcount Output [expr int(ceil((log($burst_target + 1))/(log(2))))]		
	add_interface_port avalon_master master_readdata readdata Input $mem_port_width
	add_interface_port avalon_master master_read read Output 1
	add_interface_port avalon_master master_readdatavalid readdatavalid Input 1
	add_interface_port avalon_master master_waitrequest waitrequest Input 1
	# | 
	# +-----------------------------------
}

どうやってこれを作った？

元の alt_vip_vfr_hw.tcl は、SOPC Builder の頃の tcl だったので、そのままでは Platform Designer では読み込めません。もちろん、tcl を一から解析して Platform Designer 用の記述にする事も可能です。しかし、それはちょっと骨が折れます。そこで、下記の手順で変換しました。

(1) Quartus II 13.1 を PC にインストールします。丁度この頃、 SOPC Builder から Qsys に切り替わる時期でしたので、SOPC Builder の tcl を Qsys でも読める機能がありました。

(2) Qsys の Component Editer でコアを開いて、閉じると、Qsys の tcl に変換してくれます。この時、気を付けないといけないのは、tcl の中に実行コード（上記のコードでは "# -- Dynamic Ports (elaboration callback) --" から下の部分）が含まれていると Component Editer で開けないので、tcl から実行コードを一旦削除した後、開く必要があります。

(3) 変換された tcl の実行コード部分を元に戻して、保存します。

これで、Platform Designer でも開ける IP コアが出来ました。ただ、全てこの方法で上手く行くかは分かりませんし、たとえ Platform Designer 上は上手く行っているように見えても、実装したコアが確実に動作するかも分かりませんので、自己責任でお願いします。