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2021-12-02 AXI Verification IPを使う (AXI4LITE)

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参考

処理の概要

  1. Vivadoでプロジェクトを新規作成
  2. Block Designを「sys」という名前で作成する
  3. Tools > Create and Package New IP ... > Create a new AXI4 peripheral
    • 設定はデフォルトのまま作成してIP化する
  4. myip_0をBlock Designに追加する
  5. AXI VIPを追加する
    1. PROTOCOLはAXI4LITEにする
  6. aclk, aresetnのピンをMake Externalする (名前をこのようにする)
  7. axi_vip_0とmyip_0を接続する
  8. Create HDL Wrapperをする
  9. Simulation Sourcesにtb.svを作成する
  10. Run Simulationをする
  11. みたいピンを波形に足す
    1. m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_wdata[31:0]
    2. s00_axi_wdata[31:0], s00_axi_rready, s00_axi_rvalid

以下の実装はQiitaの記事からimport axi_vip_pkgを変更している (参考2).

tb.sv
`timescale 1ns/1ps
//import axi_vip_v1_0_1_pkg::*;
import axi_vip_pkg::*;
import sys_axi_vip_0_0_pkg::*;

module tb();

    localparam int LP_CLK_PERI = 100;
    localparam int LP_RST_PERI = 777;

    // DUT instance
    logic aresetn, aclk;
    sys_wrapper dut(.*);

    task rst_gen();
        aresetn = '0;
        #(LP_RST_PERI);
        aresetn = '1;
    endtask

    task clk_gen();
        aclk = '0;
        forever #(LP_CLK_PERI/2) aclk = ~aclk;
    endtask

    task clk_dly(int n);
        repeat(n) @(posedge aclk);
    endtask

    // VIP decreation
    sys_axi_vip_0_0_mst_t   agent;

    task init_agent();
        agent = new("master vip agent", dut.sys_i.axi_vip_0.inst.IF);
        agent.start_master();
    endtask

    // Transaction method
    task wr_tran();
        axi_transaction  wr_transaction;
        wr_transaction   = agent.wr_driver.create_transaction( "write transaction with randomization");
        WR_TRANSACTION_FAIL: assert(wr_transaction.randomize());
        agent.wr_driver.send(wr_transaction);
    endtask

    task rd_tran();
        axi_transaction  rd_transaction;
        rd_transaction   = agent.rd_driver.create_transaction("read transaction with randomization");
        RD_TRANSACTION_FAIL_1a:assert(rd_transaction.randomize());
        agent.rd_driver.send(rd_transaction);
    endtask

    // Testscenario
    initial begin

        fork
            init_agent();
            clk_gen();
            rst_gen();
        join_none

        clk_dly(100);

        wr_tran();

        clk_dly(100);

        rd_tran();

        clk_dly(100);
        $finish(2);
    end
endmodule

波形の例

m_axi_wdata[31:0]に書き込まれた2f2391d9がs00_axi_rdata[31:0]に読み込まれているので、AXIの通信が成功している?
image.png (28.7 kB)

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