Zybo > Chronicles blog 21 > PS / PL interconnected > Master AXI ports / Slave AXI ports / Slave High Performance Ports / 64-bit Slave ACP / clocks from PS to PL / PS to PL Interrupts / PL to PS Interrupts / DMA peripheral request interfaces

MicroZed Chronicles リスト http://adiuvoengineering.com/?page_id=285
@ Adam Taylor blog
https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-One-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/418935

The Zynq PS and PL are interconnected via the following interfaces:

• Two 32-bit Master AXI ports (PS master)
• Two 32-bit Slave AXI ports (PL Master)
• Four 32/64-bit Slave High Performance Ports (PL Master)
• One 64-bit Slave Accelerator Coherency Port (ACP) (PL Master)
• Four clocks from the PS to the PL
• PS to PL Interrupts
• PL to PS Interrupts
• DMA peripheral request interfaces

これらを全て試すのはいつになるやら。