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chisel

Last updated at Posted at 2020-04-23

chiselで、仕事のverilog生成を楽にできないか考えて取り組み中

なんとか形になった気がするので、一応公開してみます。
必要箇所だけ抜粋したので、elaborateエラーが出るかもしれません。
出たら教えてください。

このconfigを読み込ますと、各信号を
io.apb_core.elements("ssp")(0).PRDATA :
のように指示できるので、for文なので、APBSELを作れるはず。

qiita.scala
package gcd
import chisel3._
import chisel3.experimental.ChiselEnum
import chisel3.experimental.{DataMirror, requireIsChiselType}
import chisel3.testers.BasicTester
import chisel3.util._
import scala.collection.immutable.ListMap
class APBSEL[Conf <: RVConfig] (conf:Conf) extends Module {
  val io = IO(new Bundle {
    val apb_master = new APBSlaveChannel
    val apb_core = new APBSlaveChannelCustom3(conf)
  })
}
class APBSlaveChannel extends Bundle {
  val  PADDR = Input(UInt(32.W))
  val  PWDATA = Input(UInt(32.W))
  val  PRDATA = Output(UInt(32.W))
  val  PSEL = Input(Bool())
  val  PENABLE = Input(Bool())
  val  PWRITE = Input(Bool())
  val  PREADY = Input(Bool())
  val  PREADYOUT = Output(Bool())
}
class APBSlaveChannelCustom3[Conf <: RVConfig](conf:Conf) extends Record {
  println(conf.insts_info)
  var elts = Array(("",0));  //OK
  conf.insts_info.foreach{ case (key,array) =>
    elts = elts :+ (key,array(0))
  }
  println(elts)
  val elements = ListMap( elts map { case (inst,num) =>
    s"$inst" -> Vec(num,Flipped((new APBSlaveChannel)))
  }:_*)
  def apply: Data = elements("APBSlaveChannel")
  override def cloneType: this.type = (new APBSlaveChannelCustom).asInstanceOf[this.type]
}

abstract class RVConfig()
{
  val ADDR_MAX_TOP = 0x40226fff
  val ADDR_MAX_TOP = 0x40226000
  val insts_info = scala.collection.mutable.LinkedHashMap[String, Array[Int]]()
  insts_info += ("uart" -> Array(4,0x40))
  insts_info += ("ssp" -> Array(4,0x40))
}
case class RV64ISynth() extends RVConfig
{
}

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