sukimasim
A SystemVerilog simulator built for learning - Created with Claude Code assistance
Overview
sukimasim is a personal learning project to understand SystemVerilog simulation internals by implementing a simulator from scratch. The primary goal was to gain deep, hands-on understanding of event-driven simulation algorithms, language semantics, and verification methodologies through actual implementation.
The key insight that motivated this project was that using Claude Code could potentially accelerate the development process significantly, allowing me to focus more on understanding concepts rather than getting bogged down in implementation details. I hypothesized that AI assistance could enhance the learning experience by:
- Enabling rapid prototyping and experimentation
- Providing immediate feedback on design decisions
- Allowing exploration of more complex features than would be feasible alone
- Creating a dialogue-based learning environment
This approach proved effective - the simulator implements a subset of the IEEE 1800-2017 standard and achieves a 98.6% pass rate on sv-tests, while providing deep insights into SystemVerilog internals throughout the development process.
Another crucial factor in the project's success was the availability of slang, an excellent SystemVerilog parsing library by Michael Popoloski. Without this high-quality parser handling the complex SystemVerilog syntax, implementing a simulator of this scope would have been significantly more challenging, if not impossible within a reasonable timeframe.
Learning Objectives Achieved
Through building this simulator, I gained hands-on understanding of:
- Event-driven simulation: How simulators schedule and execute events
- Language implementation: Parsing, IR generation, and interpretation
- Verification features: Constraint solving, randomization, and assertions
- SystemVerilog semantics: The intricacies of the IEEE 1800-2017 standard
- Software architecture: Designing a complex system with multiple subsystems
Development Experience with Claude Code
The entire project was developed using Claude Code, which transformed the learning experience by providing:
- Code generation: Over 47,000 lines of original C++ code developed with AI assistance
- Architecture guidance: Design decisions and implementation strategies
- Debugging support: Identifying and resolving complex issues
- Test development: Creating comprehensive test suites
The simulator achieved:
- 98.6% pass rate on sv-tests benchmark
- 1,140+ tests passing across multiple test suites
- Functional implementation of core SystemVerilog features
Key Features
- Basic SystemVerilog language constructs (modules, always blocks, tasks, functions)
- Class-based object-oriented programming support
- Constrained random verification features
- Immediate assertions
- File I/O operations
- VCD and FST waveform generation
- Basic UVM support
- DPI-C interface
Current Status
- ✅ Basic language features (IEEE 1800-2017 Chapters 5-13)
- ✅ Classes and OOP (Chapter 8)
- ✅ Processes and threads (Chapter 9)
- ✅ System tasks and functions (Chapter 20-21)
- ✅ Compiler directives (Chapter 22)
- ⚠️ Partial: Assertions (Chapter 16)
- ⚠️ Partial: Constrained randomization (Chapter 18)
- ❌ Not implemented: Coverage (Chapter 19)
- ❌ Not implemented: Functional coverage
Test Results (as of 2025-07-19):
- sv-tests: 1023/1037 tests passing (98.6%)
- Unit tests: 102/102 tests passing (100%)
- Regression tests: 15/29 tests passing (51.7%)
- Real world tests: 6/6 tests passing (100%)
- Overall: 1140/1174 tests passing (97.1%)
Building from Source
Prerequisites
- Compiler: Clang 21+ or GCC 14+ (C++20 support required)
- Build System: CMake 4.0+
-
Libraries:
- slang (SystemVerilog parsing library) v8.1
- CLI11 (command line parsing)
- Verilator (for UVM preprocessing)
- Python: 3.13+ (for testing and utilities)
Build Instructions
# Clone the repository
git clone https://github.com/yourusername/sukimasim.git
cd sukimasim
# Create build directory
mkdir build && cd build
# Configure (downloads dependencies automatically)
cmake .. -DCMAKE_BUILD_TYPE=Release
# Build
make -j32
# Run tests
make test
# Install (optional)
sudo make install
Usage
Basic usage:
# Run a SystemVerilog file
sukimasim test.sv
# With waveform generation
sukimasim test.sv --vcd output.vcd
# With UVM support
sukimasim --enable-uvm test.sv
# With seed for randomization
sukimasim --seed 12345 test.sv
Development with Claude Code
This project explored various aspects of AI-assisted development:
What Worked Well
- Architecture Design: Claude Code assisted with the event-driven simulation engine design
- Algorithm Implementation: Various algorithms including constraint solving were developed with AI support
- Debugging: AI assistance helped identify and resolve issues
- Test Development: Test suites were created with AI collaboration
- Documentation: Documentation was written with AI assistance
Lessons Learned
- Iterative Development: Breaking down complex features into smaller tasks worked best
- Context Management: Regular summarization helped maintain project coherence
- Verification: AI-generated code should always be thoroughly tested
- Human Oversight: While AI assistance was invaluable, human judgment remained essential
Project Structure
sukimasim/
├── include/sukimasim/ # Header files
├── src/ # Source files
│ ├── frontend/ # Parsing and AST→IR conversion
│ ├── ir/ # Intermediate representation
│ ├── eval/ # Simulation engine
│ └── constraint/ # Constraint solver
├── tests/ # Test suites
├── tools/ # Utility scripts
└── docs/ # Documentation
Contributing
Contributions are welcome! Please see CONTRIBUTING.md for guidelines.
License
This project is licensed under the MIT License - see LICENSE for details.
Acknowledgments
Special thanks to:
-
Michael Popoloski for creating slang, the exceptional SystemVerilog parsing library that made this project possible. The quality and completeness of slang cannot be overstated - it handles the full complexity of SystemVerilog with remarkable accuracy.
-
Claude Code from Anthropic, which served as an invaluable AI coding assistant throughout the entire development process.
-
sv-tests contributors (SymbiFlow project) for providing a comprehensive SystemVerilog test suite that enabled rigorous validation.
-
Verilator team (Wilson Snyder and contributors) for their open-source SystemVerilog simulator, which we use for UVM preprocessing.
Disclaimer
This is a personal learning project and not intended for production use. For production SystemVerilog simulation needs, please use established commercial or open-source simulators.
Built with ❤️ and Claude Code