概要
AVRの命令の組み立て方を調査してみた。
デコーダーを作るため。
Atmel AVR instruction set overview
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | d | d | d | d | r | r | r | r | MOVW Rd,Rr Move register pair |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | d | d | d | d | r | r | r | r | MULS Rd,Rr |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | d | d | d | 0 | r | r | r | MULSU Rd,Rr |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | d | d | d | 1 | r | r | r | FMUL Rd,Rr |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | d | d | d | u | r | r | r | FMULS(U) Rd,Rr |
| 0 | 0 | 0 | c̅y̅ | 0 | 1 | r | d | d | d | d | d | r | r | r | r | CPC/CP Rd,Rr |
| 0 | 0 | 0 | c̅y̅ | 1 | 0 | r | d | d | d | d | d | r | r | r | r | SBC/SUB Rd,Rr |
| 0 | 0 | 0 | cy | 1 | 1 | r | d | d | d | d | d | r | r | r | r | ADD/ADC Rd,Rr (LSL/ROL Rd when Rd=Rr) |
| 0 | 0 | 0 | 1 | 0 | 0 | r | d | d | d | d | d | r | r | r | r | CPSE Rd,Rr |
| 0 | 0 | 1 | 0 | 0 | 0 | r | d | d | d | d | d | r | r | r | r | AND Rd,Rr |
| 0 | 0 | 1 | 0 | 0 | 1 | r | d | d | d | d | d | r | r | r | r | EOR Rd,Rr |
| 0 | 0 | 1 | 0 | 1 | 0 | r | d | d | d | d | d | r | r | r | r | OR Rd,Rr |
| 0 | 0 | 1 | 0 | 1 | 1 | r | d | d | d | d | d | r | r | r | r | MOV Rd,Rr |
| 0 | 0 | 1 | 1 | K | K | K | K | d | d | d | d | K | K | K | K | CPI Rd,K |
| 0 | 1 | 0 | c̅y̅ | K | K | K | K | d | d | d | d | K | K | K | K | SBCI/SUBI Rd,K |
| 0 | 1 | 1 | 0 | K | K | K | K | d | d | d | d | K | K | K | K | ORI Rd,K SBR Rd,K |
| 0 | 1 | 1 | 1 | K | K | K | K | d | d | d | d | K | K | K | K | ANDI Rd,K CBR Rd,K |
| 1 | 0 | k | 0 | k | k | s | d | d | d | d | d | y | k | k | k | LDD/STD Rd through Z+k or Y+k |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | 0 | 0 | 0 | 0 | LDS rd,i/STS i,rd 16-Bit immediate SRAM address i |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | y | 0 | 0 | 1 | LD/ST Rd through Z+/Y+ |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | y | 0 | 1 | 0 | LD/ST Rd through −Z/−Y |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | d | d | d | d | d | 0 | 1 | q | 0 | LPM/ELPM Rd,Z |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | d | d | d | d | d | 0 | 1 | q | 1 | LPM/ELPM Rd,Z+ |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d | d | d | d | d | 0 | 1 | 0 | 0 | XCH Z,Rd |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d | d | d | d | d | 0 | 1 | 0 | 1 | LAS Z,Rd |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d | d | d | d | d | 0 | 1 | 1 | 0 | LAC Z,Rd |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d | d | d | d | d | 0 | 1 | 1 | 1 | LAT Z,Rd |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | 1 | 1 | 0 | 0 | LD/ST Rd through X |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | 1 | 1 | 0 | 1 | LD/ST Rd through X+ |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | 1 | 1 | 1 | 0 | LD/ST Rd through −X |
| 1 | 0 | 0 | 1 | 0 | 0 | s | d | d | d | d | d | 1 | 1 | 1 | 1 | POP/PUSH Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 0 | 0 | 0 | COM Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 0 | 0 | 1 | NEG Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 0 | 1 | 0 | SWAP Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 0 | 1 | 1 | INC Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 1 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 1 | 0 | 1 | ASR Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 1 | 1 | 0 | LSR Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 0 | 1 | 1 | 1 | ROR Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | B̅ | b | b | b | 1 | 0 | 0 | 0 | SEx/CLx Status register clear/set bit |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | RET |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | RETI |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | x | 1 | 0 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | x | x | 1 | 0 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | SLEEP |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | BREAK |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | WDR |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | q | 1 | 0 | 0 | 0 | LPM/ELPM |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | SPM |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | SPM Z+ |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | c | 0 | 0 | 0 | e | 1 | 0 | 0 | 1 | Indirect jump/call to Z or EIND:Z |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d | d | d | d | d | 1 | 0 | 1 | 0 | DEC Rd |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | k | k | k | k | 1 | 0 | 1 | 1 | DES round k |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | k | k | k | k | k | 1 | 1 | c | k | JMP/CALL abs22 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | k | k | p | p | k | k | k | k | ADIW Rp,uimm6 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | k | k | p | p | k | k | k | k | SBIW Rp,uimm6 |
| 1 | 0 | 0 | 1 | 1 | 0 | B | 0 | a | a | a | a | a | b | b | b | CBI/SBI a,b (clear/set I/O bit) |
| 1 | 0 | 0 | 1 | 1 | 0 | B | 1 | a | a | a | a | a | b | b | b | SBIC/SBIS a,b (I/O bit test) |
| 1 | 0 | 0 | 1 | 1 | 1 | r | d | d | d | d | d | r | r | r | r | MUL, unsigned: R1:R0 = Rr × Rd |
| 1 | 0 | 1 | 1 | s | a | a | d | d | d | d | d | a | a | a | a | IN/OUT to I/O space |
| 1 | 1 | 0 | c | 12 bit | signed | RJMP/RCALL to PC + simm12 | ||||||||||
| 1 | 1 | 1 | 0 | K | K | K | K | d | d | d | d | K | K | K | K | LDI Rd,K |
| 1 | 1 | 1 | 1 | 0 | B̅ | 7 bit | signed | b | b | b | Conditional branch on status register bit | |||||
| 1 | 1 | 1 | 1 | 1 | 0 | s | d | d | d | d | d | 0 | b | b | b | BLD/BST register bit to STATUS.T |
| 1 | 1 | 1 | 1 | 1 | 1 | B | d | d | d | d | d | 0 | b | b | b | SBRC/SBRS skip if register bit equals B |
| 1 | 1 | 1 | 1 | 1 | x | x | d | d | d | d | d | 1 | b | b | b | (reserved) |
以上。