windowsでiverilog その26

概要

windowsでiverilogやってみた。
bcdcounter書いてみる。

サンプルコード

module bcd(input clk, input rst, input inc, output reg [3:0] dg2, output reg [3:0] dg1, output reg [3:0] dg0);
	always @(posedge clk)
	begin
		if (rst)
		begin
			dg2 <= 4'b0;
			dg1 <= 4'b0;
			dg0 <= 4'b0;
		end
		else if (inc)
		begin
			if (dg0 != 4'd9)
			begin
				dg0 <= dg0 + 1'b1;
			end
			else
			begin
				dg0 <= 4'd0;
				if (dg1 != 4'd9)
				begin
					dg1 <= dg1 + 1'b1;
				end
				else
				begin
					dg1 <= 4'd0;
					dg2 <= dg2 + 1'b1;
				end
			end
		end
	end
endmodule

module test();
	reg clk;
	reg rst;
	reg inc;
	wire [3:0] dg2,
		dg1,
		dg0;
	bcd u(.clk(clk), .rst(rst), .inc(inc), .dg2(dg2), .dg1(dg1), .dg0(dg0));
	initial
	begin
		$monitor("%b %b %b %h %h", clk, rst, inc, dg1, dg0);
		clk = 0;
		rst = 0;
		inc = 0;
		#10
			rst = 1;
		#10
			rst = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			inc = 1;
		#10
			inc = 0;
		#10
			$finish;
	end
	always
	begin
		#5
			clk = 1;
		#5
			clk = 0;
	end
endmodule

実行結果

0 0 0 x x
1 0 0 x x
0 1 0 x x
1 1 0 0 0
0 0 0 0 0
1 0 0 0 0
0 0 1 0 0
1 0 1 0 1
0 0 0 0 1
1 0 0 0 1
0 0 1 0 1
1 0 1 0 2
0 0 0 0 2
1 0 0 0 2
0 0 1 0 2
1 0 1 0 3
0 0 0 0 3
1 0 0 0 3
0 0 1 0 3
1 0 1 0 4
0 0 0 0 4
1 0 0 0 4
0 0 1 0 4
1 0 1 0 5
0 0 0 0 5
1 0 0 0 5
0 0 1 0 5
1 0 1 0 6
0 0 0 0 6
1 0 0 0 6
0 0 1 0 6
1 0 1 0 7
0 0 0 0 7
1 0 0 0 7
0 0 1 0 7
1 0 1 0 8
0 0 0 0 8
1 0 0 0 8
0 0 1 0 8
1 0 1 0 9
0 0 0 0 9
1 0 0 0 9
0 0 1 0 9
1 0 1 1 0
0 0 0 1 0
1 0 0 1 0
0 0 0 1 0