windowsでiverilog その119

概要　

windowsでiverilogやってみた。
picやってみた。

参考にしたページ。

アセンブラ

ORG 0
	BSF   	STATUS, RP0
	CLRF  	TRISA
	CLRF  	TRISB
	MOVLW 	B'00000001'
	MOVWF 	PORTB
	BCF   	STATUS, RP0
LOOP
	MOVLW 	B'00000000'
	MOVWF 	H'05'
	MOVLW 	B'00000001'
	MOVWF 	H'05'
	goto 	LOOP
	END

サンプルコード

module PrgRom(clk, romaddr, romout);
	input clk;
	input [12:0] romaddr;
	output [13:0] romout;
	function [13:0] rom;
		input [12:0] addr;
		case (addr)
		13'h0000: rom = 14'h1683;
		13'h0001: rom = 14'h0185;
		13'h0002: rom = 14'h0186;
		13'h0003: rom = 14'h3001;
		13'h0004: rom = 14'h0086;
		13'h0005: rom = 14'h1283;
		13'h0006: rom = 14'h3000;
		13'h0007: rom = 14'h0085;
		13'h0008: rom = 14'h3001;
		13'h0009: rom = 14'h0085;
		13'h000A: rom = 14'h2806;
		13'h000B: rom = 14'h3400;
		13'h000C: rom = 14'h3400;
		13'h000D: rom = 14'h3fff;
		13'h000E: rom = 14'h3fff;
		13'h000F: rom = 14'h3fff;
		default: rom = 14'h3FFF;
		endcase
	endfunction
	reg [13:0] r_RomOut;
	assign romout = r_RomOut;
	always @(negedge clk)
	begin
		r_RomOut <= rom(romaddr);
	end
endmodule

module Top;
	parameter STEP = 1;
	reg r_Clk;
	reg r_Reset;
	reg r_RxD;
	wire w_RxD;
	wire [3:0] w_RA;
	wire [7:0] w_RB;
	wire [12:0] PC = tm.w_PC;
	wire [13:0] Inst = tm.w_Inst;
	wire [8:0] RamAddr = tm.w_RamAddr;
	wire RamWE = tm.w_RamWE;
	wire [5:0] RA = tm.r_RA;
	wire [7:0] RB = tm.r_RB;
	wire [7:0] RC = tm.w_RC;
	wire [7:0] PicDataIn = tm.w_PicDataIn;
	wire [7:0] PicDataOut = tm.w_PicDataOut;
	wire T0I = tm.r_T0I;
	wire [4:0] ST = tm.pic.r_ST;
	wire [13:0] I = tm.pic.r_I;
	wire [7:0] W = tm.pic.r_W;
	wire [2:0] SP = tm.pic.r_SP;
	wire [7:0] STATUS = tm.pic.r_STATUS;
	wire [7:0] FSR = tm.pic.r_FSR;
	wire [4:0] PCLATH = tm.pic.r_PCLATH;
	wire [7:0] INTCON = tm.pic.r_INTCON;
	wire [7:0] DataIn = tm.pic.r_DataIn;
	wire [7:0] AluOut = tm.pic.w_AluOut;
	wire CF = tm.pic.w_AluCF;
	wire DC = tm.pic.w_AluDC;
	wire ZF = tm.pic.w_AluZF;
	wire IncPC = tm.pic.w_IncPC;
	wire [15:0] TMR0 = tm.r_TMR0;
	wire [7:0] OPTION = tm.r_OPTION;
	wire w_branch = tm.pic.w_branch;
	TestModule tm(r_Clk, r_Reset, r_RxD, w_RxD, w_RA, w_RB);
	always
		#(STEP)
			r_Clk <= ~r_Clk;
	initial
	begin
		//$dumpfile("wave.vcd");
		//$dumpvars(1, Top);
		$monitor("%d %h %h %h", PC, RA, RB, RC);
		r_RxD = 1;
		r_Reset = 1;
		r_Clk = 1;
		#3
			r_Reset = 0;
		#(STEP * 200)
			$finish;
	end
endmodule

結果

   0 00 00 00
   1 00 00 00
   2 00 00 00
   3 00 00 00
   4 00 00 00
   5 00 00 00
   6 00 00 00
   7 00 00 00
   8 00 00 00
   9 00 00 00
  10 00 00 00
  11 01 00 00
   6 01 00 00
   7 01 00 00
   8 01 00 00
   9 00 00 00
  10 00 00 00
  11 01 00 00
   6 01 00 00
   7 01 00 00
   8 01 00 00
   9 00 00 00
  10 00 00 00
  11 01 00 00
   6 01 00 00
   7 01 00 00
   8 01 00 00
   9 00 00 00
  10 00 00 00

以上。