paiza.ioでelixir その74

概要

paiza.ioでelixirやってみた。
FPGAの高位合成書いてみた。
７セグメント・デコーダ書いてみた。

高位合成て何

FPGAを記述する、HDL言語を生成するコンパイラ
下のコードから下の下のコードを生成する。

lut 12
lin 4
lout 8
code 0 7E
code 1 30
code 2 6d
code 3 79
code 4 33
code 5 5b
code 6 5f
code 7 72
code 8 7f
code 9 7b

module lut(input wire [3:0] data, output reg [7:0] code);
    always @(data)
    begin
        case(data)
        4'h0: code = 8'h7E;
        4'h1: code = 8'h30;
        4'h2: code = 8'h6d;
        4'h3: code = 8'h79;
        4'h4: code = 8'h33;
        4'h5: code = 8'h5b;
        4'h6: code = 8'h5f;
        4'h7: code = 8'h72;
        4'h8: code = 8'h7f;
        4'h9: code = 8'h7b;
        endcase
    end
endmodule

module testbench;
    reg [3:0] data;
    wire [7:0] code;
    lut u(.data(data), .code(code));
    initial
    begin
        $display("data code");
        $monitor("%h  %h", data, code);
        data = 4'h0; #10;
        data = 4'h1; #10;
        data = 4'h2; #10;
        data = 4'h3; #10;
        data = 4'h4; #10;
        data = 4'h5; #10;
        data = 4'h6; #10;
        data = 4'h7; #10;
        data = 4'h8; #10;
        data = 4'h9; #10;
        $finish;
    end
endmodule

シミュレーション結果

>iverilog lut.v

>vvp a.out
data code
0  7e
1  30
2  6d
3  79
4  33
5  5b
6  5f
7  72
8  7f
9  7b

サンプルコード

defmodule Asm do
	def start_link do
		Agent.start_link(fn ->
			%{u: ""}
		end, name: __MODULE__)
	end
    def code(a, b) do
		Agent.update(__MODULE__, fn v ->
            str = "        4'h" <> a <> ": code = 8'h" <> b <> ";\n"
            %{v | u: v.u <> str}
		end)
    end
    def print() do
		Agent.get(__MODULE__, fn v ->
            IO.puts "module lut(input wire [3:0] data, output reg [7:0] code);\n" <>
	        "    always @(data)\n" <>
	        "    begin\n" <>
		    "        case(data)\n" <>
		    v.u <>
		    "        endcase\n" <>
	        "    end\n" <>
		    "endmodule\n\n" <>
		    "module testbench;\n" <>
            "    reg [3:0] data;\n" <>
	        "    wire [7:0] code;\n" <>
	        "    lut u(.data(data), .code(code));\n" <>
	        "    initial\n" <>
	        "    begin\n" <>
		    "        $display(\"data code\");\n" <>
		    "        $monitor(\"%h  %h\", data, code);\n" <>
		    "        data = 4'h0; #10;\n" <>
		    "        data = 4'h1; #10;\n" <>
		    "        data = 4'h2; #10;\n" <>
		    "        data = 4'h3; #10;\n" <>
		    "        data = 4'h4; #10;\n" <>
		    "        data = 4'h5; #10;\n" <>
		    "        data = 4'h6; #10;\n" <>
		    "        data = 4'h7; #10;\n" <>
		    "        data = 4'h8; #10;\n" <>
		    "        data = 4'h9; #10;\n" <>
		    "        $finish;\n" <>
	        "    end\n" <>
            "endmodule\n"

		end)
	end
end

defmodule Main do
	def run(str) do
    	Enum.map(String.split(str, "\n"), fn l ->
		    s = String.split(l, " ")
		    cond do
				Enum.at(s, 0) == "code" ->
					Asm.code(Enum.at(s, 1), Enum.at(s, 2))
				true ->
					IO.puts ""
			end
	    end)
	    Asm.print
	end
end

Asm.start_link

Main.run("""
lut 12
lin 4
lout 8
code 0 7E
code 1 30
code 2 6d
code 3 79
code 4 33
code 5 5b
code 6 5f
code 7 72
code 8 7f
code 9 7b
""")

成果物

以上。