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高位合成言語アセンブラを作る。 その21

Last updated at Posted at 2021-03-15

概要

高位合成言語アセンブラを作る。
俺言語から、verilogコードを生成する。

コードを投入。

九九

10 a=1
20 b=1
30 ?=a*b
60 a=a+1
70 #=a<10*30
90 b=b+1
100 a=1
110 #=b<10*30
120 #=120

生成したコード

module ore(input clk, input rst, output reg [7:0] out);
	reg [7:0] a;
	reg [7:0] b;
	reg [7:0] pc;
	always @(posedge clk)
	begin
		if (!rst)
		begin
			a <= 0;
			b <= 0;
			pc <= 10;
		end
		else
		begin
			case (pc)
			10:
			begin
				a <= 1;
				pc <= 20;
			end
			20:
			begin
				b <= 1;
				pc <= 30;
			end
			30:
			begin
				out <= a*b;
				pc <= 60;
			end
			60:
			begin
				a <= a+1;
				pc <= 70;
			end
			70:
			begin
				if (a<10)
				begin
					pc <= 30;
				end
				else
				begin
					pc <= 90;
				end
			end
			90:
			begin
				b <= b+1;
				pc <= 100;
			end
			100:
			begin
				a <= 1;
				pc <= 110;
			end
			110:
			begin
				if (b<10)
				begin
					pc <= 30;
				end
				else
				begin
					pc <= 120;
				end
			end
			120:
			begin
				pc <= 120;
			end
  			endcase
		end
	end
endmodule
module test;
	reg clk,
		rst;
	wire [7:0] out;
	ore u(.clk(clk), .rst(rst), .out(out));
	initial
	begin
		clk = 0;
		rst = 1;
		$monitor("%d", out);
		#2
			rst = 0;
		#2
			rst = 1;
		#2500
			$finish;
	end
	always
		#1
			clk = ~clk;
endmodule

成果物

以上。

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