windowsでiverilog その22

概要

windowsでiverilogやってみた。
stack書いてみる。

サンプルコード

module stack(top_out, next_out, top_in, next_in, pop, push, w_tos, w_next, clk, rst);
	output [15:0] top_out,
		next_out;
	input [15:0] top_in,
		next_in;
	input pop,
		push,
		w_tos,
		w_next,
		clk,
		rst;
	reg [15:0] top_out,
		next_out;
	reg [15:0] stack_ram[31:0];
	reg [4:0] tos_position,
		next_position;
	always @(posedge clk or posedge rst)
	begin
		if (rst == 1)
		begin
			tos_position = 5'b0;
			next_position = 5'b11111;
		end
		else if (clk == 1)
		begin
			if (pop == 1)
			begin
				tos_position = tos_position - 1;
				next_position = next_position - 1;
			end
			else if (push == 1)
			begin
				tos_position = tos_position + 1;
				next_position = next_position + 1;
			end
			if (w_tos == 1)
				stack_ram[tos_position] = top_in;
			if (w_next == 1)
				stack_ram[next_position] = next_in;
			top_out = stack_ram[tos_position];
			next_out = stack_ram[next_position];
		end
	end
endmodule

module test;
	reg [15:0] top_in;
	reg [15:0] next_in;
	reg pop;
	reg push;
	reg w_tos;
	reg w_next;
	reg clk;
	reg rst;
	wire [15:0] top_out;
	wire [15:0] next_out;
	stack u(.top_out(top_out), .next_out(next_out), .top_in(top_in), .next_in(next_in), .pop(pop), .push(push), .w_tos(w_tos), .w_next(w_next), .clk(clk), .rst(rst));
	initial
	begin
		$display("clk rst in out");
		$monitor("%b %b %h %h", clk, rst, top_in, top_out);
		top_in = 0;
		next_in = 0;
		pop = 0;
		push = 0;
		w_tos = 0;
		w_next = 0;
		clk = 0;
		rst = 0;
		#10
			rst = 1;
		#10
			rst = 0;
		#10
			top_in = 16'b1100110011001100;
			w_tos = 1;
		#10
			top_in = 16'b0011001100110011;
			push = 1;
		#10
			top_in = 16'b0011100110100101;
		#10
			top_in = 16'b1011001110001111;
		#10
			w_tos = 0;
			pop = 1;
		#10
			next_in = 16'b1111111100000000;
			w_next = 1;
			pop = 0;
		#10
			$finish;
	end
	always
	begin
		#5
			clk = 1;
		#5
			clk = 0;
	end
endmodule

実行結果

clk rst in out
0 0 0000 xxxx
1 0 0000 xxxx
0 1 0000 xxxx
1 1 0000 xxxx
0 0 0000 xxxx
1 0 0000 xxxx
0 0 cccc xxxx
1 0 cccc cccc
0 0 3333 cccc
1 0 3333 3333
0 0 39a5 3333
1 0 39a5 39a5
0 0 b38f 39a5
1 0 b38f b38f
0 0 b38f b38f
1 0 b38f 39a5
0 0 b38f 39a5
1 0 b38f b38f
0 0 b38f b38f

以上。