概要

VHDLをverilogに変換してみた。

環境

wsl(wsl2じゃない)
windows11
ubuntu22.04

インストール手順

git clone https://github.com/YosysHQ/yosys.git
cd yosys
make config-clang
git submodule update --init
make -j$(nproc)
sudo make install

git clone https://github.com/ghdl/ghdl.git
cd ghdl
./configure --prefix=/usr/local
make -j$(nproc)
sudo make install

git clone https://github.com/ghdl/ghdl-yosys-plugin.git
cd ghdl-yosys-plugin
make GHDL=/usr/local/bin/ghdl -j$(nproc)
sudo make GHDL=/usr/local/bin/ghdl install

動作確認

test.vhd

library IEEE;
use IEEE.std_logic_1164.all;
entity ORing is
port (A, B: in std_logic; Y: out std_logic);
end ORing;
architecture RTL of ORing is
begin
        Y <= A or B;
end;

変換スクリプト

$ yosys -m ghdl -p 'ghdl test.vhd -e ORing; write_verilog test.v'

実行結果


 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.44+60 (git sha1 72f77dd97, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `ghdl test.vhd -e ORing; write_verilog test.v' --

1. Executing GHDL.
Importing module ORing.

2. Executing Verilog backend.

2.1. Executing BMUXMAP pass.

2.2. Executing DEMUXMAP pass.
Dumping module `\ORing'.

End of script. Logfile hash: ac7f4e6e39, CPU: user 0.04s system 0.01s, MEM: 17.77 MB peak
Yosys 0.44+60 (git sha1 72f77dd97, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 90% 1x ghdl (0 sec), 5% 2x write_verilog (0 sec), ...

生成されたverilog


/* Generated by Yosys 0.44+60 (git sha1 72f77dd97, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3) */

module ORing(A, B, Y);
  wire _0_;
  input A;
  wire A;
  input B;
  wire B;
  output Y;
  wire Y;
  assign _0_ = A | B;
  assign Y = _0_;
endmodule

以上。