Vivado 2020.2.2 でPost-Synthesis Simulationが[XSIM 43-3255], [XSIM 43-3217], [USF-XSim-62]で停止する場合の対処法

#エラー内容

TCL_console

INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '<Project>/<Project>.tmp/<IP>_ip_v1_0_project/<IP>_ip_v1_0_project.sim/sim_1/synth/func/xsim'
xvlog --incr --relax -prj testbench_1_vlog.prj
ERROR: [XSIM 43-3255] File name is missing.
ERROR: [XSIM 43-3217] testbench_1_vlog.prj (line 3): Incorrect project file syntax. Correct syntax is one of: vhdl <worklib> <file>, verilog <worklib> <file> [<file> ...] [[-d <macro>] ...] [[-i <include>] ...], or NOSORT. Presence of NOSORT on a line of its own disables file order sorting.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'<Project>/<Project>.tmp/<IP>_ip_v1_0_project/<IP>_ip_v1_0_project.sim/sim_1/synth/func/xsim/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '<Project>/<Project>.tmp/<IP>_ip_v1_0_project/<IP>_ip_v1_0_project.sim/sim_1/synth/func/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

..../sim_1/synth/func/xsim/xvlog.log

# compile verilog/system verilog design source files
verilog xil_defaultlib  \
"testbench_1_func_synth.v" \

verilog   \
"../../../../../../../../ip_repo/<IP>_ip_1.0/hdl/testbench.v" \

# Do not sort compile order
nosort
~

#対処法
https://support.xilinx.com/s/question/0D52E00006iHilWSAS/error-xsim-433217-incorrect-project-file-syntax-even-with-a-library-selected?language=ja

Testbenchのソースコードにライブラリが設定されていなかったのが原因

ここでxil_defaultlibに設定することでシミュレーションが走り出した。

(検索用：Google検索が[]内のキーワードを拾ってくれないので)
XSIM 43-3255
XSIM 43-3217
USF-XSim-62
Vivado 12-4473
Common 17-39