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[VHDL]numeric_stdライブラリを使った時のinteger⇔std_logic_vectorの変換方法

Last updated at Posted at 2022-04-08

ライブラリのソースを見に行くのが面倒臭いので備忘録として残しておく

使用ライブラリ

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

変換コード

signal s_stdlogicvector : std_logic_vector(9 downto 0) := (others => '0');
signal s_integer : integer range 0 to 1023 := 0;

-- std_logic_vector ⇒ integer
s_integer <= to_integer(unsigned(s_stdlogicvector)); -- unsignedとして扱いたい時
s_integer <= to_integer(signed(s_stdlogicvector)); -- signedとして扱いたい時

-- integer ⇒ std_logic_vector
s_stdlogicvector <= std_logic_vector(to_unsigned(s_integer, s_stdlogicvector'length));
s_stdlogicvector <= std_logic_vector(to_signed(s_integer, s_stdlogicvector'length));
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