[VHDL]VSCodeでVHDLを書く時に登録しておくと便利なスニペット

ファイル→ユーザー設定→ユーザースニペットの構成　から以下の新規スニペットを作成

vhdl.json

{
	"process": {
		"prefix": "process (my snippet)",
		"body": [
			"process(CLK)",
			"begin",
			"\tif (RST='1') then",
			"\t\t",
			"\telsif (rising_edge(CLK)) then",
			"\t\t",
			"\tend if;",
			"end process;"
		]
	},
	"component": {
		"prefix": "component (my snippet)",
		"body": [
			"component $1 is port (",
			"\t",
			"); end component $1;"
		]
	},
	"entity": {
		"prefix": "entity (my snippet)",
		"body": [
			"entity $TM_FILENAME_BASE is",
			"\tport (",
			"\t\tCLK : in std_logic;",
			"\t\tRST : in std_logic;",
			"\t\t",
			"\t);",
			"end entity $TM_FILENAME_BASE;"
		]
	},
	"instance": {
		"prefix": "instance (my snippet)",
		"body": [
			"$1_Inst : $1 port map(",
			"\t",
			");"
		]
	},
	"architecture": {
		"prefix": "architecture (my snippet)",
		"body": [
			"architecture rtl of $TM_FILENAME_BASE is",
			"\t$1",
			"begin",
			"\t",
			"end architecture rtl;"
		]
	}
}