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[SystemVerilog]packed構造体のrand_mode

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HDLあどべんが瀕死なので前にハマった事をちょいと書きます。
ただあまり考察できてない内容なので間違いがあるかもしれませんがご容赦ください。

SystemVerilogでたまに構造体を使うのですがランダムと組み合わせて使った時にハマりました。

配列にしろ、構造体にしろpackedの方が何かとサボれるので何も考えずにpackedにするのですが
下記のコードのようにrandをつけて宣言した場合、構造体のメンバ個別のrand_modeのON/OFFができなくなります。

test1.sv
`timescale 1ns/1ps

typedef struct packed {
  logic [3:0] hoge;
  logic [7:0] fuga;
} my_st1;

module test1();

  class my_class;
    rand my_st1 st1;

    constraint c_st1_hoge { st1.hoge >= 4'h8;  }
    constraint c_st1_fuga { st1.fuga >= 8'h88; }

    function new(logic [3:0] st1_hoge, logic [7:0] st1_fuga);
      this.st1.hoge = st1_hoge;
      this.st1.fuga = st1_fuga;
    endfunction : new

  endclass : my_class

  initial begin
    // 1st
    my_class c = new(4'h0, 8'h00);
    $display("1st: hoge = 0x%01h, fuga = 0x%02h", c.st1.hoge, c.st1.fuga);

    // 2nd
    void'(c.randomize());
    $display("2nd: hoge = 0x%01h, fuga = 0x%02h", c.st1.hoge, c.st1.fuga);

    // 3rd
    c.st1      = 12'h111;
    $display("3rd: hoge = 0x%01h, fuga = 0x%02h", c.st1.hoge, c.st1.fuga);

    // 4th
    c.constraint_mode(0);
    c.st1.rand_mode(0);
    void'(c.randomize());
    $display("4th: hoge = 0x%01h, fuga = 0x%02h", c.st1.hoge, c.st1.fuga);

    // 5th
    c.st1.rand_mode(1);
    c.constraint_mode(1);
    c.c_st1_hoge.constraint_mode(0);
    c.st1.hoge.rand_mode(0);
    void'(c.randomize());
    $display("5th: hoge = 0x%01h, fuga = 0x%02h", c.st1.hoge, c.st1.fuga);

    $finish(2);
  end

endmodule : test1

実行結果

1st: hoge = 0x0, fuga = 0x00
2nd: hoge = 0xd, fuga = 0xcb
3rd: hoge = 0x1, fuga = 0x11
4th: hoge = 0x1, fuga = 0x11
5th: hoge = 0x2, fuga = 0x95

構造体じゃなくてバスの信号でも、各bit個別のrand_mode ON/OFFができないということを考えれば、
まぁ当たり前のことかもしれません。

そう、当たり前のことなんですよ。きっと、、、

じゃあエラーにしろよ!!!

シミュレータによってはエラーになるのですが、
私がよく使っているシミュレータでは何も言わずに通りました。

まぁね、こんな記述するほうが悪いのかもしれないんだけど。
一言ぐらい言ってくれてもいいじゃない・・・
構造体使わないかもしれないけど使うときにはご注意を。

imatatsu
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