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@eggman

RISC-Vのアセンブリ記述

More than 1 year has passed since last update.

RISC-Vのアセンブリ記述について

ちょこっとRISC-Vのアセンブリ記述を調べたメモです。

まだ、中途半端ですが…

ドキュメント

いまのところ、網羅的な情報はみつからないので、必要になったらgccで生成したアセンブリ記述を調べています。

演算

a5レジスタに即値12を加算

  addi a5, a5, 12

a4 = a4 + a3

  add a4, a4, a3

a4 = a4 * a3

  mul a4, a4, a3

代入

a0 = a4

  mv a0, a4

メモリ操作

レジスタraの値をsp+8番地のメモリにストア

  sd ra,8(sp)

sp+8番地のメモリの値をレジスタraにロード

  ld ra,8(sp)

擬似命令

L1にジャンプ

  j L1
L1:
  ret

リターン

  ret

即値ロード

  li a0 4

即値ロードはアセンブラでaddiに変換される。

  addi a0, zero, 4

呼び出し規約

  • 関数の引数はa0, a1, a2, a3, a4, a5 にセット
  • 関数の戻り値はa0にセット
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